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vsim intro

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This commit is contained in:
Jan Decaluwe 2010-09-11 23:15:09 +02:00
parent 1a438778b9
commit 71123d8996
6 changed files with 21 additions and 1 deletions
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5
.hgignore
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@ -3,6 +3,8 @@ syntax: glob
.pydevproject
CHANGELOG.txt
MANIFEST
modelsim.ini
transcript
*~
*.pyc
*.swp
@ -18,9 +20,12 @@ MANIFEST
*.vcd
*.0
*.bak
*.wlf
doc/build
build/
dist/
old_conversion/
work/
work_vlog/
work_vcom/

3
myhdl/test/conversion/general/vcom.py Normal file
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@ -0,0 +1,3 @@
from myhdl.conversion import verify, analyze
verify.simulator = analyze.simulator = "vcom"

3
myhdl/test/conversion/general/vlog.py Normal file
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@ -0,0 +1,3 @@
from myhdl.conversion import verify, analyze
verify.simulator = analyze.simulator = "vlog"

5
myhdl/test/conversion/toVerilog2/Makefile
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@ -1,4 +1,7 @@
all: cver
all: vlog
vlog:
py.test vlog.py test_*.py
icarus:
py.test icarus.py test_*.py

3
myhdl/test/conversion/toVerilog2/vcom.py Normal file
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@ -0,0 +1,3 @@
from myhdl.conversion import verify, analyze
verify.simulator = analyze.simulator = "vcom"

3
myhdl/test/conversion/toVerilog2/vlog.py Normal file
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@ -0,0 +1,3 @@
from myhdl.conversion import verify, analyze
verify.simulator = analyze.simulator = "vlog"