diff --git a/.hgignore b/.hgignore
index ddee3987..bf23d96d 100644
--- a/.hgignore
+++ b/.hgignore
@@ -3,6 +3,8 @@ syntax: glob
 .pydevproject
 CHANGELOG.txt
 MANIFEST
+modelsim.ini
+transcript
 *~
 *.pyc
 *.swp
@@ -18,9 +20,12 @@ MANIFEST
 *.vcd
 *.0
 *.bak
+*.wlf
 doc/build
 build/
 dist/
 old_conversion/
 work/
 work_vlog/
+work_vcom/
+
diff --git a/myhdl/test/conversion/general/vcom.py b/myhdl/test/conversion/general/vcom.py
new file mode 100644
index 00000000..bc0fb727
--- /dev/null
+++ b/myhdl/test/conversion/general/vcom.py
@@ -0,0 +1,3 @@
+from myhdl.conversion import verify, analyze
+
+verify.simulator = analyze.simulator = "vcom"
diff --git a/myhdl/test/conversion/general/vlog.py b/myhdl/test/conversion/general/vlog.py
new file mode 100644
index 00000000..62ffbd67
--- /dev/null
+++ b/myhdl/test/conversion/general/vlog.py
@@ -0,0 +1,3 @@
+from myhdl.conversion import verify, analyze
+
+verify.simulator = analyze.simulator = "vlog"
diff --git a/myhdl/test/conversion/toVerilog2/Makefile b/myhdl/test/conversion/toVerilog2/Makefile
index cdfa7be1..08cd0117 100644
--- a/myhdl/test/conversion/toVerilog2/Makefile
+++ b/myhdl/test/conversion/toVerilog2/Makefile
@@ -1,4 +1,7 @@
-all: cver 
+all: vlog  
+
+vlog:
+	py.test vlog.py test_*.py
 
 icarus:
 	py.test icarus.py test_*.py
diff --git a/myhdl/test/conversion/toVerilog2/vcom.py b/myhdl/test/conversion/toVerilog2/vcom.py
new file mode 100644
index 00000000..bc0fb727
--- /dev/null
+++ b/myhdl/test/conversion/toVerilog2/vcom.py
@@ -0,0 +1,3 @@
+from myhdl.conversion import verify, analyze
+
+verify.simulator = analyze.simulator = "vcom"
diff --git a/myhdl/test/conversion/toVerilog2/vlog.py b/myhdl/test/conversion/toVerilog2/vlog.py
new file mode 100644
index 00000000..62ffbd67
--- /dev/null
+++ b/myhdl/test/conversion/toVerilog2/vlog.py
@@ -0,0 +1,3 @@
+from myhdl.conversion import verify, analyze
+
+verify.simulator = analyze.simulator = "vlog"