loop tests

myhdl/_toVerilog.py

@@ -715,6 +715,7 @@ class _ConvertVisitor(_ToVerilogMixin):
     def __init__(self, ast, buf):
         self.buf = buf
         self.name = ast.name
+        self.returnLabel = self.name
         self.sourcefile = ast.sourcefile
         self.lineoffset = ast.lineoffset
         self.sigdict = ast.sigdict
@@ -750,7 +751,7 @@ class _ConvertVisitor(_ToVerilogMixin):
     def dedent(self):
         self.ind = self.ind[:-4]
 
-    def binaryOp(self, node, op):
+    def binaryOp(self, node, op=None):
         self.write("(")
         self.visit(node.left)
         self.write(" %s " % op)
@@ -1068,7 +1069,7 @@ class _ConvertVisitor(_ToVerilogMixin):
         self.write("$finish;")
         
     def visitReturn(self, node):
-        self.write("disable %s;" % self.name)
+        self.write("disable %s;" % self.returnLabel)
 
     def visitRightShift(self, node):
         self.binaryOp(node, '>>')
@@ -1133,9 +1134,8 @@ class _ConvertVisitor(_ToVerilogMixin):
         self.labelStack.append(node.breakLabel)
         self.labelStack.append(node.loopLabel)
         if node.breakLabel.isActive:
-            self.writeline()
             self.write("begin: %s" % node.breakLabel)
-        self.writeline()
+            self.writeline()
         self.write("while (")
         self.visit(node.test)
         self.write(") begin")
@@ -1297,7 +1297,7 @@ class _ConvertTaskVisitor(_ConvertVisitor):
         self.writeDeclarations()
         self.dedent()
         self.writeline()
-        self.write("begin")
+        self.write("begin: %s" % self.returnLabel)
         self.indent()
         self.visit(node.code)
         self.dedent()
@@ -1307,5 +1307,3 @@ class _ConvertTaskVisitor(_ConvertVisitor):
         self.write("endtask")
         self.writeline(2)
 
-    
-    

myhdl/test/toVerilog/test_loops.py

@@ -5,7 +5,7 @@ from random import randrange
 
 from myhdl import *
 
-def ForLoop(a, out):
+def ForLoop1(a, out):
     while 1:
         yield a
         var = 0
@@ -13,7 +13,52 @@ def ForLoop(a, out):
             if a[i] == 1:
                 var += 1
         out.next = var
+
+def ForLoop2(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in downrange(len(a), 5):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForLoop3(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in downrange(len(a), 3, 2):
+            if a[i] == 1:
+                var += 1
+        out.next = var
         
+def ForLoop4(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in range(len(a)):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForLoop5(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in range(6, len(a)):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForLoop6(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in range(5, len(a), 3):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
 def ForContinueLoop(a, out):
     while 1:
         yield a
@@ -183,8 +228,28 @@ class TestLoops(unittest.TestCase):
 
         return stimulus(), looptest_inst, looptest_v_inst
 
-    def testForLoop(self):
-        sim = self.bench(ForLoop)
+    def testForLoop1(self):
+        sim = self.bench(ForLoop1)
+        Simulation(sim).run()
+        
+    def testForLoop2(self):
+        sim = self.bench(ForLoop2)
+        Simulation(sim).run()
+        
+    def testForLoop3(self):
+        sim = self.bench(ForLoop3)
+        Simulation(sim).run()
+        
+    def testForLoop4(self):
+        sim = self.bench(ForLoop4)
+        Simulation(sim).run()
+        
+    def testForLoop5(self):
+        sim = self.bench(ForLoop5)
+        Simulation(sim).run()
+        
+    def testForLoop6(self):
+        sim = self.bench(ForLoop6)
         Simulation(sim).run()
         
     def testForContinueLoop(self):