diff --git a/myhdl/_ShadowSignal.py b/myhdl/_ShadowSignal.py
index 370cad75..6631980e 100644
--- a/myhdl/_ShadowSignal.py
+++ b/myhdl/_ShadowSignal.py
@@ -406,6 +406,9 @@ class _TristateSignal(_ShadowSignal):
                 lines.append("%s <= %s;" % (self._name, d._name))
         return "\n".join(lines)
 
+    def __repr__(self):
+        return "_TristateSignal(" + repr(self._val) + ")"
+
 
 class _TristateDriver(_Signal):
 
@@ -428,3 +431,6 @@ class _TristateDriver(_Signal):
             self._next = self._sig._orival
             self._setNextVal(val)
         _siglist.append(self)
+
+    def __repr__(self):
+        return "_TristateDriver(" + repr(self._val) + ")"
diff --git a/myhdl/__init__.py b/myhdl/__init__.py
index cc8b8331..9807128c 100644
--- a/myhdl/__init__.py
+++ b/myhdl/__init__.py
@@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
 toVerilog -- function that converts a design to Verilog
 
 """
-__version__ = "0.11.49"
+__version__ = "0.11.50"
 
 
 class StopSimulation(Exception):
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index 22e32b00..8359fd1b 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -475,25 +475,21 @@ def _writeSigDecls(f, intf, siglist, memlist):
 
             sig_vhdl_obj = inferVhdlObj(s)
 
-            if not toVHDL.initial_values:
-                val_str = ""
-            else:
-
-                if isinstance(sig_vhdl_obj, vhd_std_logic):
+            val_str = ''
+            if toVHDL.initial_values:
+                if isinstance(s, _TristateSignal):
+                    # a TriState signal has no initial value
+                    # one might argue that 'Z' could be appropriate?
+                    pass
+                elif isinstance(sig_vhdl_obj, vhd_std_logic):
                     # Single bit
                     val_str = " := '%s'" % int(s._init)
                 elif isinstance(sig_vhdl_obj, vhd_int):
                     val_str = " := %s" % s._init
                 elif isinstance(sig_vhdl_obj, (vhd_signed, vhd_unsigned)):
-                    val_str = ' := %dX"%s"' % (
-                        sig_vhdl_obj.size, str(s._init))
-
+                    val_str = ' := %dX"%s"' % (sig_vhdl_obj.size, str(s._init))
                 elif isinstance(sig_vhdl_obj, vhd_enum):
-                    val_str = ' := %s' % (s._init,)
-
-                else:
-                    # default to no initial value
-                    val_str = ''
+                    val_str = ' := %s' % s._init
 
             print("signal %s: %s%s%s;" % (s._name, p, r, val_str), file=f)