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blocked intialstaion of TristateSignals (#439)

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Josy Boelen 2024-08-07 20:24:32 +02:00 committed by GitHub
parent e3b4d5263a
commit 75bb3a7598
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3 changed files with 16 additions and 14 deletions
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6
myhdl/_ShadowSignal.py
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@ -406,6 +406,9 @@ class _TristateSignal(_ShadowSignal):
lines.append("%s <= %s;" % (self._name, d._name)) lines.append("%s <= %s;" % (self._name, d._name))
return "\n".join(lines) return "\n".join(lines)
def __repr__(self):
return "_TristateSignal(" + repr(self._val) + ")"
class _TristateDriver(_Signal): class _TristateDriver(_Signal):
@ -428,3 +431,6 @@ class _TristateDriver(_Signal):
self._next = self._sig._orival self._next = self._sig._orival
self._setNextVal(val) self._setNextVal(val)
_siglist.append(self) _siglist.append(self)
def __repr__(self):
return "_TristateDriver(" + repr(self._val) + ")"

2
myhdl/__init__.py
View File

@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
toVerilog -- function that converts a design to Verilog toVerilog -- function that converts a design to Verilog
""" """
__version__ = "0.11.49" __version__ = "0.11.50"
class StopSimulation(Exception): class StopSimulation(Exception):

22
myhdl/conversion/_toVHDL.py
View File

@ -475,25 +475,21 @@ def _writeSigDecls(f, intf, siglist, memlist):
sig_vhdl_obj = inferVhdlObj(s) sig_vhdl_obj = inferVhdlObj(s)
if not toVHDL.initial_values: val_str = ''
val_str = "" if toVHDL.initial_values:
else: if isinstance(s, _TristateSignal):
# a TriState signal has no initial value
if isinstance(sig_vhdl_obj, vhd_std_logic): # one might argue that 'Z' could be appropriate?
pass
elif isinstance(sig_vhdl_obj, vhd_std_logic):
# Single bit # Single bit
val_str = " := '%s'" % int(s._init) val_str = " := '%s'" % int(s._init)
elif isinstance(sig_vhdl_obj, vhd_int): elif isinstance(sig_vhdl_obj, vhd_int):
val_str = " := %s" % s._init val_str = " := %s" % s._init
elif isinstance(sig_vhdl_obj, (vhd_signed, vhd_unsigned)): elif isinstance(sig_vhdl_obj, (vhd_signed, vhd_unsigned)):
val_str = ' := %dX"%s"' % ( val_str = ' := %dX"%s"' % (sig_vhdl_obj.size, str(s._init))
sig_vhdl_obj.size, str(s._init))
elif isinstance(sig_vhdl_obj, vhd_enum): elif isinstance(sig_vhdl_obj, vhd_enum):
val_str = ' := %s' % (s._init,) val_str = ' := %s' % s._init
else:
# default to no initial value
val_str = ''
print("signal %s: %s%s%s;" % (s._name, p, r, val_str), file=f) print("signal %s: %s%s%s;" % (s._name, p, r, val_str), file=f)