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conversion bug from IPROBE project

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jand 2007-12-20 13:53:23 +00:00
parent 454b2294df
commit 77a0d8c1d4
5 changed files with 7 additions and 5 deletions
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2
CHANGES.txt
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@ -1,4 +1,4 @@
Release 0.6dev5
Release 0.6dev6
---------------
Release 0.5.1 1-May-2006

2
README.txt
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@ -1,4 +1,4 @@
MyHDL Release 0.6dev5
MyHDL Release 0.6dev6
=====================
OVERVIEW

2
myhdl/__init__.py
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@ -48,7 +48,7 @@ __author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
__revision__ = "$Revision$"
__date__ = "$Date$"
__version__ = "0.6dev5"
__version__ = "0.6dev6"
import sys
import warnings

4
myhdl/conversion/_toVHDL.py
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@ -366,7 +366,8 @@ class _ConvertVisitor(_ConversionMixin):
pre, suf = "resize(", ", %s)" % vhd.size
elif isinstance(ori, vhd_signed):
if vhd.size != ori.size:
pre, suf = "unsigned(resize(", ", %s))" % vhd.size
# note the order of resizing and casting here (otherwise bug!)
pre, suf = "resize(unsigned(", "), %s)" % vhd.size
else:
pre, suf = "unsigned(", ")"
else:
@ -377,6 +378,7 @@ class _ConvertVisitor(_ConversionMixin):
pre, suf = "resize(", ", %s)" % vhd.size
elif isinstance(ori, vhd_unsigned):
if vhd.size != ori.size:
# I think this should be the order of resizing and casting here
pre, suf = "signed(resize(", ", %s))" % vhd.size
else:
pre, suf = "signed(", ")"

2
setup.py
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@ -32,7 +32,7 @@ Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
setup(name="myhdl",
version="0.6dev5",
version="0.6dev6",
description="Python as a Hardware Description Language",
long_description = "See home page.",
author="Jan Decaluwe",