From 77de13ac669fe90dedd4ce7526aeabb85a800a4c Mon Sep 17 00:00:00 2001
From: Jan Decaluwe <jan@jandecaluwe.com>
Date: Tue, 12 Aug 2014 16:15:21 +0200
Subject: [PATCH] Fixed issue #10 (2)

---
 myhdl/conversion/_toVHDL.py        |  2 ++
 myhdl/test/bugs/test_issue_10.py   | 24 ++++++++++++++++++
 myhdl/test/bugs/test_issue_10_1.py | 40 ++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 myhdl/test/bugs/test_issue_10.py
 create mode 100644 myhdl/test/bugs/test_issue_10_1.py

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index 03024811..e5d7c689 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -2009,6 +2009,8 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
             for a in node.args:
                 if isinstance(a, ast.Str):
                     a.vhd = vhd_unsigned(a.vhd.size)
+                elif isinstance(a.vhd, vhd_signed):
+                    a.vhd = vhd_unsigned(a.vhd.size) 
                 s += a.vhd.size
             node.vhd = vhd_unsigned(s)
         elif f is bool:
diff --git a/myhdl/test/bugs/test_issue_10.py b/myhdl/test/bugs/test_issue_10.py
new file mode 100644
index 00000000..90cd595b
--- /dev/null
+++ b/myhdl/test/bugs/test_issue_10.py
@@ -0,0 +1,24 @@
+#!/usr/bin/python2.7-32
+# -*- coding: utf-8 -*-
+
+import myhdl
+
+def unsigned(width, value=0, cls=myhdl.intbv):
+     """Create an unsigned signal based on a bitvector with the
+     specified width and initial value.
+     """
+     return myhdl.Signal(cls(value, 0, 2**width))
+
+def signed(width, value=0, cls=myhdl.intbv):
+     """Create an signed signal based on a bitvector with the
+     specified width and initial value.
+     """
+     return myhdl.Signal(cls(value, -2**(width-1), 2**(width-1)))
+
+a = unsigned(4, 8)
+b = signed(28, -3)
+
+#print "%08X" % myhdl.concat(a, b)
+#print hex(myhdl.concat(a, b))
+def test_issue_10():
+    assert myhdl.concat(a, b) == 0x8ffffffd
diff --git a/myhdl/test/bugs/test_issue_10_1.py b/myhdl/test/bugs/test_issue_10_1.py
new file mode 100644
index 00000000..fd8cadf6
--- /dev/null
+++ b/myhdl/test/bugs/test_issue_10_1.py
@@ -0,0 +1,40 @@
+#!/usr/bin/python2.7-32
+# -*- coding: utf-8 -*-
+"""Failed VHDL code example
+"""
+
+from myhdl import *
+from myhdl.conversion import verify
+
+def unsigned(width, value=0, cls=intbv):
+    """Create an unsigned signal based on a bitvector with the
+    specified width and initial value.
+    """
+    return Signal(cls(value, 0, 2**width))
+
+def signed(width, value=0, cls=intbv):
+    """Create an signed signal based on a bitvector with the
+    specified width and initial value.
+    """
+    return Signal(cls(value, -2**(width-1), 2**(width-1)))
+
+
+flags = unsigned(4)
+position = signed(28)
+
+def Logic(flags, position):
+
+    conc = unsigned(32)
+
+    @instance
+    def doit():
+        flags.next = 4 
+        position.next = 28
+        yield delay(10)
+        conc.next = concat(flags, position)
+        yield delay(10)
+        print conc 
+    return doit
+
+def test_issue_10_1():
+    assert verify(Logic, flags, position) == 0