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jand
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77
myhdl/test/toVHDL/test_bin2gray.py
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77
myhdl/test/toVHDL/test_bin2gray.py
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import os
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path = os.path
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from myhdl import *
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from myhdl.test import verifyConversion
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def bin2gray2(B, G, width):
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""" Gray encoder.
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B -- input intbv signal, binary encoded
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G -- output intbv signal, gray encoded
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width -- bit width
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"""
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Bext = intbv(0)[width+1:]
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while 1:
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yield B
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Bext[:] = B
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for i in range(width):
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G.next[i] = Bext[i+1] ^ Bext[i]
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def bin2gray(B, G, width):
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""" Gray encoder.
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B -- input intbv signal, binary encoded
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G -- output intbv signal, gray encoded
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width -- bit width
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"""
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@always_comb
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def logic():
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Bext = intbv(0)[width+1:]
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Bext[:] = B
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for i in range(width):
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G.next[i] = Bext[i+1] ^ Bext[i]
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return logic
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def bin2grayBench(width, bin2gray):
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B = Signal(intbv(0)[width:])
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G = Signal(intbv(0)[width:])
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bin2gray_inst = bin2gray(B, G, width)
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n = 2**width
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@instance
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def stimulus():
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for i in range(n):
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B.next = i
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yield delay(10)
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#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
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#print bin(G, width)
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#print bin(G_v, width)
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print G
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return stimulus, bin2gray_inst
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## def test1(self):
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## sim = self.bench(width=8, bin2gray=bin2gray)
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## Simulation(sim).run()
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## def test2(self):
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## sim = self.bench(width=8, bin2gray=bin2gray2)
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## Simulation(sim).run()
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verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray)
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verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray2)
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158
myhdl/test/toVHDL/test_hec.py
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158
myhdl/test/toVHDL/test_hec.py
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import os
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path = os.path
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from random import randrange
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from myhdl import *
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from myhdl.test import verifyConversion
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COSET = 0x55
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def calculateHecRef(header):
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""" Return hec for an ATM header.
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Reference version.
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The hec polynomial is 1 + x + x**2 + x**8.
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"""
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hec = intbv(0)
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for bit in header[32:]:
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hec[8:] = concat(hec[7:2],
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bit ^ hec[1] ^ hec[7],
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bit ^ hec[0] ^ hec[7],
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bit ^ hec[7]
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)
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return hec ^ COSET
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def calculateHecFunc(header):
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""" Return hec for an ATM header.
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Translatable version.
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The hec polynomial is 1 + x + x**2 + x**8.
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"""
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h = intbv(0)[8:]
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for i in downrange(len(header)):
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bit = header[i]
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h[:] = concat(h[7:2],
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bit ^ h[1] ^ h[7],
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bit ^ h[0] ^ h[7],
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bit ^ h[7]
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)
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h ^= COSET
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return h
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def calculateHecTask(hec, header):
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""" Calculate hec for an ATM header.
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Translatable version.
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The hec polynomial is 1 + x + x**2 + x**8.
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"""
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h = intbv(0)[8:]
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for i in downrange(len(header)):
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bit = header[i]
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h[:] = concat(h[7:2],
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bit ^ h[1] ^ h[7],
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bit ^ h[0] ^ h[7],
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bit ^ h[7]
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)
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h ^= COSET
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hec[:] = h
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def HecCalculatorPlain(hec, header):
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""" Hec calculation module.
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Plain version.
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"""
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h = intbv(0)[8:]
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while 1:
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yield header
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h[:] = 0
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for i in downrange(len(header)):
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bit = header[i]
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h[:] = concat(h[7:2],
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bit ^ h[1] ^ h[7],
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bit ^ h[0] ^ h[7],
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bit ^ h[7]
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)
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hec.next = h ^ COSET
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def HecCalculatorFunc(hec, header):
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""" Hec calculation module.
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Version with function call.
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"""
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h = intbv(0)[8:]
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while 1:
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yield header
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hec.next = calculateHecFunc(header=header)
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def HecCalculatorTask(hec, header):
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""" Hec calculation module.
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Version with task call.
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"""
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h = intbv(0)[8:]
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while 1:
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yield header
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calculateHecTask(h, header)
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hec.next = h
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def HecCalculatorTask2(hec, header):
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""" Hec calculation module.
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Version with task call.
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"""
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h = intbv(0)[8:]
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while 1:
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yield header
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calculateHecTask(header=header, hec=h)
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hec.next = h
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def HecCalculator_v(name, hec, header):
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return setupCosimulation(**locals())
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headers = [ 0x00000000L,
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0x01234567L,
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0xbac6f4caL
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]
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headers.extend([randrange(2**32-1) for i in range(10)])
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headers = tuple(headers)
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def HecBench(HecCalculator):
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hec = Signal(intbv(0)[8:])
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hec_v = Signal(intbv(0)[8:])
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header = Signal(intbv(-1)[32:])
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heccalc_inst = HecCalculator(hec, header)
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@instance
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def stimulus():
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for i in range(len(headers)):
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header.next = headers[i]
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yield delay(10)
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print hec
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return stimulus, heccalc_inst
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## def testPlain(self):
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## sim = self.bench(HecCalculatorPlain)
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## Simulation(sim).run()
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## def testFunc(self):
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## sim = self.bench(HecCalculatorFunc)
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## Simulation(sim).run()
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## def testTask(self):
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## sim = self.bench(HecCalculatorTask)
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## Simulation(sim).run()
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## def testTask2(self):
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## sim = self.bench(HecCalculatorTask2)
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## Simulation(sim).run()
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verifyConversion(HecBench, HecCalculatorPlain)
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301
myhdl/test/toVHDL/test_loops.py
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301
myhdl/test/toVHDL/test_loops.py
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import os
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path = os.path
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import unittest
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from random import randrange
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from myhdl import *
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from util import setupCosimulation
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def ForLoop1(a, out):
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while 1:
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yield a
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var = 0
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for i in downrange(len(a)):
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if a[i] == 1:
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var += 1
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out.next = var
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def ForLoop2(a, out):
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while 1:
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yield a
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var = 0
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for i in downrange(len(a), 5):
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if a[i] == 1:
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var += 1
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out.next = var
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def ForLoop3(a, out):
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while 1:
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yield a
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var = 0
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for i in downrange(len(a), 3, 2):
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if a[i] == 1:
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var += 1
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out.next = var
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def ForLoop4(a, out):
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while 1:
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yield a
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var = 0
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for i in range(len(a)):
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if a[i] == 1:
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var += 1
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out.next = var
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def ForLoop5(a, out):
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while 1:
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yield a
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var = 0
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for i in range(6, len(a)):
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if a[i] == 1:
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var += 1
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out.next = var
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def ForLoop6(a, out):
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while 1:
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yield a
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var = 0
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for i in range(5, len(a), 3):
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if a[i] == 1:
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var += 1
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out.next = var
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def ForContinueLoop(a, out):
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while 1:
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yield a
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var = 0
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for i in downrange(len(a)):
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if a[i] == 0:
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continue
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var += 1
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out.next = var
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def ForBreakLoop(a, out):
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while 1:
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yield a
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out.next = 0
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for i in downrange(len(a)):
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if a[i] == 1:
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out.next = i
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break
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def ForBreakContinueLoop(a, out):
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while 1:
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yield a
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out.next = 0
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for i in downrange(len(a)):
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if a[i] == 0:
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continue
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out.next = i
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break
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def NestedForLoop1(a, out):
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while 1:
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yield a
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var = 0
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for i in downrange(len(a)):
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if a[i] == 0:
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continue
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else:
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for j in downrange(i):
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if a[j] == 0:
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var +=1
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break
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out.next = var
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def NestedForLoop2(a, out):
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while 1:
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yield a
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var = 0
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out.next = 0
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for i in downrange(len(a)):
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if a[i] == 0:
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continue
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else:
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for j in downrange(i-1):
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if a[j] == 0:
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pass
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else:
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out.next = j
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break
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break
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def ReturnFromFunction(a):
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for i in downrange(len(a)):
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if a[i] == 1:
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return i
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return 0
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def FunctionCall(a, out):
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while 1:
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yield a
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out.next = ReturnFromFunction(a)
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# During the following check, I noticed that non-blocking assignments
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# are not scheduled when a task is disabled in Icarus. Apparently
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# this is one of the many vague areas in the Verilog standard.
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def ReturnFromTask(a, out):
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for i in downrange(len(a)):
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if a[i] == 1:
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out[:] = i
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return
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out[:] = 23 # to notice it
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def TaskCall(a, out):
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var = intbv(0)[8:]
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while 1:
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yield a
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ReturnFromTask(a, var)
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out.next = var
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def WhileLoop(a, out):
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while 1:
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yield a
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var = 0
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i = len(a)-1
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while i >= 0:
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if a[i] == 1:
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var += 1
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i -= 1
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out.next = var
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def WhileContinueLoop(a, out):
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while 1:
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yield a
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var = 0
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i = len(a)-1
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while i >= 0:
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if a[i] == 0:
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i -= 1
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continue
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var += 1
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i -= 1
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out.next = var
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def WhileBreakLoop(a, out):
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while 1:
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yield a
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var = 0
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i = len(a)-1
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out.next = 0
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while i >= 0:
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if a[i] == 1:
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out.next = i
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break
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i -= 1
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def WhileBreakContinueLoop(a, out):
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while 1:
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yield a
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var = 0
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i = len(a)-1
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out.next = 0
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while i >= 0:
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if a[i] == 0:
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i -= 1
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continue
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out.next = i
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break
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def LoopTest_v(name, a, out):
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return setupCosimulation(**locals())
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class TestLoops(unittest.TestCase):
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def bench(self, LoopTest):
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a = Signal(intbv(-1)[16:])
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out_v = Signal(intbv(0)[16:])
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out = Signal(intbv(0)[16:])
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looptest_inst = toVerilog(LoopTest, a, out)
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# looptest_inst = LoopTest(hec, header)
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looptest_v_inst = LoopTest_v(LoopTest.func_name, a, out_v)
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def stimulus():
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for i in range(100):
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a.next = randrange(2**min(i, 16))
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yield delay(10)
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# print "%s %s" % (out, out_v)
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self.assertEqual(out, out_v)
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return stimulus(), looptest_inst, looptest_v_inst
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def testForLoop1(self):
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sim = self.bench(ForLoop1)
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Simulation(sim).run()
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def testForLoop2(self):
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sim = self.bench(ForLoop2)
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Simulation(sim).run()
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def testForLoop3(self):
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sim = self.bench(ForLoop3)
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Simulation(sim).run()
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def testForLoop4(self):
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sim = self.bench(ForLoop4)
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Simulation(sim).run()
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def testForLoop5(self):
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sim = self.bench(ForLoop5)
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Simulation(sim).run()
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def testForLoop6(self):
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sim = self.bench(ForLoop6)
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Simulation(sim).run()
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def testForContinueLoop(self):
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sim = self.bench(ForContinueLoop)
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Simulation(sim).run()
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def testForBreakLoop(self):
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sim = self.bench(ForBreakLoop)
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Simulation(sim).run()
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def testForBreakContinueLoop(self):
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sim = self.bench(ForBreakContinueLoop)
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Simulation(sim).run()
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def testNestedForLoop1(self):
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sim = self.bench(NestedForLoop1)
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Simulation(sim).run()
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def testNestedForLoop2(self):
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sim = self.bench(NestedForLoop2)
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Simulation(sim).run()
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def testNestedForLoop2(self):
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sim = self.bench(NestedForLoop2)
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Simulation(sim).run()
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def testFunctionCall(self):
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sim = self.bench(FunctionCall)
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Simulation(sim).run()
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def testTaskCall(self):
|
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sim = self.bench(TaskCall)
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Simulation(sim).run()
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def testWhileLoop(self):
|
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sim = self.bench(WhileLoop)
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Simulation(sim).run()
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def testWhileContinueLoop(self):
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sim = self.bench(WhileContinueLoop)
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Simulation(sim).run()
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def testWhileBreakLoop(self):
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sim = self.bench(WhileBreakLoop)
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Simulation(sim).run()
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def testWhileBreakContinueLoop(self):
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sim = self.bench(WhileBreakContinueLoop)
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Simulation(sim).run()
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|
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|
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if __name__ == '__main__':
|
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unittest.main()
|
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