diff --git a/myhdl/test/toVHDL/test_bin2gray.py b/myhdl/test/toVHDL/test_bin2gray.py
new file mode 100644
index 00000000..e7bcbc40
--- /dev/null
+++ b/myhdl/test/toVHDL/test_bin2gray.py
@@ -0,0 +1,77 @@
+import os
+path = os.path
+
+from myhdl import *
+from myhdl.test import verifyConversion
+
+def bin2gray2(B, G, width):
+    """ Gray encoder.
+
+    B -- input intbv signal, binary encoded
+    G -- output intbv signal, gray encoded
+    width -- bit width
+    """
+    Bext = intbv(0)[width+1:]
+    while 1:
+        yield B
+        Bext[:] = B
+        for i in range(width):
+            G.next[i] = Bext[i+1] ^ Bext[i]
+
+def bin2gray(B, G, width):
+    
+    """ Gray encoder.
+
+    B -- input intbv signal, binary encoded
+    G -- output intbv signal, gray encoded
+    width -- bit width
+    
+    """
+
+    @always_comb
+    def logic():
+        Bext = intbv(0)[width+1:]
+        Bext[:] = B
+        for i in range(width):
+            G.next[i] = Bext[i+1] ^ Bext[i]
+
+    return logic
+           
+      
+ 
+def bin2grayBench(width, bin2gray):
+
+    B = Signal(intbv(0)[width:])
+    G = Signal(intbv(0)[width:])
+
+    bin2gray_inst = bin2gray(B, G, width)
+
+    n = 2**width
+
+    @instance
+    def stimulus():
+        for i in range(n):
+            B.next = i
+            yield delay(10)
+            #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
+            #print bin(G, width)
+            #print bin(G_v, width)
+            print G
+
+
+    return stimulus, bin2gray_inst
+
+
+
+##     def test1(self):
+##         sim = self.bench(width=8, bin2gray=bin2gray)
+##         Simulation(sim).run()
+        
+##     def test2(self):
+##         sim = self.bench(width=8, bin2gray=bin2gray2)
+##         Simulation(sim).run()
+    
+
+verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray)
+verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray2)
+
diff --git a/myhdl/test/toVHDL/test_hec.py b/myhdl/test/toVHDL/test_hec.py
new file mode 100644
index 00000000..25fd029c
--- /dev/null
+++ b/myhdl/test/toVHDL/test_hec.py
@@ -0,0 +1,158 @@
+import os
+path = os.path
+from random import randrange
+
+from myhdl import *
+from myhdl.test import verifyConversion
+
+COSET = 0x55
+
+def calculateHecRef(header):
+    """ Return hec for an ATM header.
+
+    Reference version.
+    The hec polynomial is 1 + x + x**2 + x**8.
+    """
+    hec = intbv(0)
+    for bit in header[32:]:
+        hec[8:] = concat(hec[7:2],
+                         bit ^ hec[1] ^ hec[7],
+                         bit ^ hec[0] ^ hec[7],
+                         bit ^ hec[7]
+                        )
+    return hec ^ COSET
+
+def calculateHecFunc(header):
+    """ Return hec for an ATM header.
+    
+    Translatable version.
+    The hec polynomial is 1 + x + x**2 + x**8.
+    """
+    h = intbv(0)[8:]
+    for i in downrange(len(header)):
+        bit = header[i]
+        h[:] = concat(h[7:2],
+                      bit ^ h[1] ^ h[7],
+                      bit ^ h[0] ^ h[7],
+                      bit ^ h[7]
+                      )
+    h ^= COSET
+    return h
+
+def calculateHecTask(hec, header):
+    """ Calculate hec for an ATM header.
+    
+    Translatable version.
+    The hec polynomial is 1 + x + x**2 + x**8.
+    """
+    h = intbv(0)[8:]
+    for i in downrange(len(header)):
+        bit = header[i]
+        h[:] = concat(h[7:2],
+                      bit ^ h[1] ^ h[7],
+                      bit ^ h[0] ^ h[7],
+                      bit ^ h[7]
+                      )
+    h ^= COSET
+    hec[:] = h
+
+def HecCalculatorPlain(hec, header):
+    """ Hec calculation module.
+
+    Plain version.
+    """
+    h = intbv(0)[8:]
+    while 1:
+        yield header
+        h[:] = 0
+        for i in downrange(len(header)):
+            bit = header[i]
+            h[:] = concat(h[7:2],
+                          bit ^ h[1] ^ h[7],
+                          bit ^ h[0] ^ h[7],
+                          bit ^ h[7]
+                          )
+        hec.next = h ^ COSET
+
+def HecCalculatorFunc(hec, header):
+    """ Hec calculation module.
+
+    Version with function call.
+    """
+    h = intbv(0)[8:]
+    while 1:
+        yield header
+        hec.next = calculateHecFunc(header=header)
+
+def HecCalculatorTask(hec, header):
+    """ Hec calculation module.
+
+    Version with task call.
+    """
+    h = intbv(0)[8:]
+    while 1:
+        yield header
+        calculateHecTask(h, header)
+        hec.next = h
+        
+def HecCalculatorTask2(hec, header):
+    """ Hec calculation module.
+
+    Version with task call.
+    """
+    h = intbv(0)[8:]
+    while 1:
+        yield header
+        calculateHecTask(header=header, hec=h)
+        hec.next = h
+
+         
+        
+def HecCalculator_v(name, hec, header):
+    return setupCosimulation(**locals())
+
+
+
+headers = [ 0x00000000L,
+            0x01234567L,
+            0xbac6f4caL
+          ]
+
+headers.extend([randrange(2**32-1) for i in range(10)])
+headers = tuple(headers)
+
+
+def HecBench(HecCalculator):
+
+    hec = Signal(intbv(0)[8:])
+    hec_v = Signal(intbv(0)[8:])
+    header = Signal(intbv(-1)[32:])
+
+    heccalc_inst = HecCalculator(hec, header)
+
+    @instance
+    def stimulus():
+        for i in range(len(headers)):
+            header.next = headers[i]
+            yield delay(10)
+            print hec
+
+    return stimulus, heccalc_inst
+
+## def testPlain(self):
+##     sim = self.bench(HecCalculatorPlain)
+##     Simulation(sim).run()
+
+## def testFunc(self):
+##     sim = self.bench(HecCalculatorFunc)
+##     Simulation(sim).run()
+
+## def testTask(self):
+##     sim = self.bench(HecCalculatorTask)
+##     Simulation(sim).run()
+
+## def testTask2(self):
+##     sim = self.bench(HecCalculatorTask2)
+##     Simulation(sim).run()
+
+verifyConversion(HecBench, HecCalculatorPlain)
diff --git a/myhdl/test/toVHDL/test_loops.py b/myhdl/test/toVHDL/test_loops.py
new file mode 100644
index 00000000..c6fbb0ef
--- /dev/null
+++ b/myhdl/test/toVHDL/test_loops.py
@@ -0,0 +1,301 @@
+import os
+path = os.path
+import unittest
+from random import randrange
+
+
+from myhdl import *
+
+from util import setupCosimulation
+
+def ForLoop1(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in downrange(len(a)):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForLoop2(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in downrange(len(a), 5):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForLoop3(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in downrange(len(a), 3, 2):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+        
+def ForLoop4(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in range(len(a)):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForLoop5(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in range(6, len(a)):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForLoop6(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in range(5, len(a), 3):
+            if a[i] == 1:
+                var += 1
+        out.next = var
+
+def ForContinueLoop(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in downrange(len(a)):
+            if a[i] == 0:
+                continue
+            var += 1
+        out.next = var
+
+def ForBreakLoop(a, out):
+    while 1:
+        yield a
+        out.next = 0
+        for i in downrange(len(a)):
+            if a[i] == 1:
+                out.next = i
+                break
+
+def ForBreakContinueLoop(a, out):
+    while 1:
+        yield a
+        out.next = 0
+        for i in downrange(len(a)):
+            if a[i] == 0:
+                continue
+            out.next = i
+            break
+
+def NestedForLoop1(a, out):
+    while 1:
+        yield a
+        var = 0
+        for i in downrange(len(a)):
+            if a[i] == 0:
+                continue
+            else:
+                for j in downrange(i):
+                    if a[j] == 0:
+                        var +=1
+                break
+        out.next = var
+
+def NestedForLoop2(a, out):
+    while 1:
+        yield a
+        var = 0
+        out.next = 0
+        for i in downrange(len(a)):
+            if a[i] == 0:
+                continue
+            else:
+                for j in downrange(i-1):
+                    if a[j] == 0:
+                        pass
+                    else:
+                        out.next = j
+                        break
+                break
+
+def ReturnFromFunction(a):
+       for i in downrange(len(a)):
+            if a[i] == 1:
+                return i
+       return 0
+
+def FunctionCall(a, out):
+    while 1:
+        yield a
+        out.next = ReturnFromFunction(a)
+
+# During the following check, I noticed that non-blocking assignments
+# are not scheduled when a task is disabled in Icarus. Apparently
+# this is one of the many vague areas in the Verilog standard.
+def ReturnFromTask(a, out):
+    for i in downrange(len(a)):
+        if a[i] == 1:
+            out[:] = i
+            return
+    out[:] = 23 # to notice it
+
+def TaskCall(a, out):
+    var = intbv(0)[8:]
+    while 1:
+        yield a
+        ReturnFromTask(a, var)
+        out.next = var
+
+def WhileLoop(a, out):
+    while 1:
+        yield a
+        var = 0
+        i = len(a)-1
+        while i >= 0:
+            if a[i] == 1:
+                var += 1
+            i -= 1
+        out.next = var
+
+def WhileContinueLoop(a, out):
+    while 1:
+        yield a
+        var = 0
+        i = len(a)-1
+        while i >= 0:
+            if a[i] == 0:
+                i -= 1
+                continue
+            var += 1
+            i -= 1
+        out.next = var
+        
+def WhileBreakLoop(a, out):
+    while 1:
+        yield a
+        var = 0
+        i = len(a)-1
+        out.next = 0
+        while i >= 0:
+            if a[i] == 1:
+                out.next = i
+                break
+            i -= 1
+    
+def WhileBreakContinueLoop(a, out):
+    while 1:
+        yield a
+        var = 0
+        i = len(a)-1
+        out.next = 0
+        while i >= 0:
+            if a[i] == 0:
+                 i -= 1
+                 continue
+            out.next = i
+            break
+    
+        
+def LoopTest_v(name, a, out):
+    return setupCosimulation(**locals())
+
+class TestLoops(unittest.TestCase):
+
+    def bench(self, LoopTest):
+        
+        a = Signal(intbv(-1)[16:])
+        out_v = Signal(intbv(0)[16:])
+        out = Signal(intbv(0)[16:])
+
+        looptest_inst = toVerilog(LoopTest, a, out)
+        # looptest_inst = LoopTest(hec, header)
+        looptest_v_inst = LoopTest_v(LoopTest.func_name, a, out_v)
+ 
+        def stimulus():
+            for i in range(100):
+                a.next = randrange(2**min(i, 16))
+                yield delay(10)
+                # print "%s %s" % (out, out_v)
+                self.assertEqual(out, out_v)
+
+        return stimulus(), looptest_inst, looptest_v_inst
+
+    def testForLoop1(self):
+        sim = self.bench(ForLoop1)
+        Simulation(sim).run()
+        
+    def testForLoop2(self):
+        sim = self.bench(ForLoop2)
+        Simulation(sim).run()
+        
+    def testForLoop3(self):
+        sim = self.bench(ForLoop3)
+        Simulation(sim).run()
+        
+    def testForLoop4(self):
+        sim = self.bench(ForLoop4)
+        Simulation(sim).run()
+        
+    def testForLoop5(self):
+        sim = self.bench(ForLoop5)
+        Simulation(sim).run()
+        
+    def testForLoop6(self):
+        sim = self.bench(ForLoop6)
+        Simulation(sim).run()
+        
+    def testForContinueLoop(self):
+        sim = self.bench(ForContinueLoop)
+        Simulation(sim).run()
+        
+    def testForBreakLoop(self):
+        sim = self.bench(ForBreakLoop)
+        Simulation(sim).run()
+        
+    def testForBreakContinueLoop(self):
+        sim = self.bench(ForBreakContinueLoop)
+        Simulation(sim).run()
+        
+    def testNestedForLoop1(self):
+        sim = self.bench(NestedForLoop1)
+        Simulation(sim).run()
+        
+    def testNestedForLoop2(self):
+        sim = self.bench(NestedForLoop2)
+        Simulation(sim).run()
+        
+    def testNestedForLoop2(self):
+        sim = self.bench(NestedForLoop2)
+        Simulation(sim).run()
+
+    def testFunctionCall(self):
+        sim = self.bench(FunctionCall)
+        Simulation(sim).run()
+        
+    def testTaskCall(self):
+        sim = self.bench(TaskCall)
+        Simulation(sim).run()
+       
+    def testWhileLoop(self):
+        sim = self.bench(WhileLoop)
+        Simulation(sim).run()
+
+    def testWhileContinueLoop(self):
+        sim = self.bench(WhileContinueLoop)
+        Simulation(sim).run()
+
+    def testWhileBreakLoop(self):
+        sim = self.bench(WhileBreakLoop)
+        Simulation(sim).run()
+        
+    def testWhileBreakContinueLoop(self):
+        sim = self.bench(WhileBreakContinueLoop)
+        Simulation(sim).run()
+
+        
+if __name__ == '__main__':
+    unittest.main()