mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
Keerthan Jaic
GitHub
commit
7b17942abb
1
.gitignore
vendored
1
.gitignore
vendored
@ -36,3 +36,4 @@ myhdl/**/*.vhd
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# Pycharm ide junk
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.idea/
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/.pytest_cache/
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@ -29,6 +29,7 @@ import inspect
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from myhdl._Cosimulation import Cosimulation
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from myhdl._instance import _Instantiator
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def _isGenSeq(obj):
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from myhdl._block import _Block
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if isinstance(obj, (Cosimulation, _Instantiator, _Block)):
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@ -682,6 +682,26 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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elif v == 1:
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node.edge = sig.posedge
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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node.obj = None # safeguarding?
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# ToDo check for tuples?
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if isinstance(node.value, int):
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# Num
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if node.value in (0, 1):
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node.obj = bool(node.value)
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else:
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node.obj = node.value
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elif node.value in (True, False, None):
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# NameConstant
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node.obj = node.value
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elif isinstance(node.value, str):
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# Str
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node.obj = node.value
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else:
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def visit_Num(self, node):
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n = node.n
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# assign to value attribute for backwards compatibility
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@ -696,6 +716,9 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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def visit_Str(self, node):
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node.obj = node.s
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def visit_NameConstant(self, node):
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node.obj = node.value
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def visit_Continue(self, node):
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self.labelStack[-1].isActive = True
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@ -787,9 +810,6 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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self.raiseError(node, _error.UnsupportedListComp)
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mem.depth = cf.args[0].obj
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def visit_NameConstant(self, node):
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node.obj = node.value
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def visit_Name(self, node):
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if isinstance(node.ctx, ast.Store):
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self.setName(node)
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@ -976,7 +996,11 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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def accessIndex(self, node):
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self.visit(node.value)
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self.access = _access.INPUT
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if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
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self.visit(node.slice)
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else:
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self.visit(node.slice.value)
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if isinstance(node.value.obj, _Ram):
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if isinstance(node.ctx, ast.Store):
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self.raiseError(node, _error.ListElementAssign)
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@ -986,7 +986,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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rhs = node.value
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# shortcut for expansion of ROM in case statement
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if isinstance(node.value, ast.Subscript) and \
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isinstance(node.value.slice, ast.Index) and \
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not isinstance(node.value.slice, ast.Slice) and \
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isinstance(node.value.value.obj, _Rom):
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rom = node.value.value.obj.rom
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self.write("case ")
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@ -1189,6 +1189,51 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.visit(right)
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self.write(suf)
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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if node.value is None:
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# NameConstant
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node.id = str(node.value)
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self.getName(node)
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elif isinstance(node.value, bool):
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# NameConstant
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node.id = str(node.value)
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self.getName(node)
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elif isinstance(node.value, int):
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# Num
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n = node.value
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if isinstance(node.vhd, vhd_std_logic):
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self.write("'%s'" % n)
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elif isinstance(node.vhd, vhd_boolean):
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self.write("%s" % bool(n))
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# elif isinstance(node.vhd, (vhd_unsigned, vhd_signed)):
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# self.write('"%s"' % tobin(n, node.vhd.size))
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elif isinstance(node.vhd, vhd_unsigned):
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if abs(n) < 2 ** 31:
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self.write("to_unsigned(%s, %s)" % (n, node.vhd.size))
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else:
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self.write('unsigned\'("%s")' % tobin(n, node.vhd.size))
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elif isinstance(node.vhd, vhd_signed):
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if abs(n) < 2 ** 31:
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self.write("to_signed(%s, %s)" % (n, node.vhd.size))
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else:
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self.write('signed\'("%s")' % tobin(n, node.vhd.size))
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else:
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if n < 0:
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self.write("(")
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self.write(n)
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if n < 0:
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self.write(")")
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elif isinstance(node.value, str):
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# Str
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typemark = 'string'
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if isinstance(node.vhd, vhd_unsigned):
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typemark = 'unsigned'
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self.write("%s'(\"%s\")" % (typemark, node.value))
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else:
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def visit_Num(self, node):
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n = node.n
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if isinstance(node.vhd, vhd_std_logic):
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@ -1220,6 +1265,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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typemark = 'unsigned'
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self.write("%s'(\"%s\")" % (typemark, node.s))
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def visit_NameConstant(self, node):
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node.id = str(node.value)
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self.getName(node)
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def visit_Continue(self, node, *args):
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self.write("next;")
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@ -1399,10 +1448,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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for stmt in node.body:
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self.visit(stmt)
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def visit_NameConstant(self, node):
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node.id = str(node.value)
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self.getName(node)
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def visit_Name(self, node):
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if isinstance(node.ctx, ast.Store):
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self.setName(node)
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@ -1470,6 +1515,8 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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s = "to_signed(%s, %s)" % (obj, node.vhd.size)
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else:
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s = 'signed\'("%s")' % tobin(obj, node.vhd.size)
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elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple
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s = n
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elif isinstance(obj, _Signal):
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s = str(obj)
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ori = inferVhdlObj(obj)
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@ -1583,6 +1630,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.visit(node.value)
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self.write("(")
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# assert len(node.subs) == 1
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if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
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self.visit(node.slice)
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else:
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self.visit(node.slice.value)
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self.write(")")
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self.write(suf)
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@ -2244,6 +2294,28 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
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right.vhd = vhd_signed(right.vhd.size + 1)
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node.vhdOri = copy(node.vhd)
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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if node.value is None:
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# NameConstant
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node.vhd = inferVhdlObj(node.value)
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elif isinstance(node.value, bool):
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# NameConstant
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node.vhd = inferVhdlObj(node.value)
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elif isinstance(node.value, int):
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# Num
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if node.value < 0:
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node.vhd = vhd_int()
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else:
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node.vhd = vhd_nat()
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elif isinstance(node.value, str):
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# Str
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node.vhd = vhd_string()
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node.vhdOri = copy(node.vhd)
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else:
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def visit_Str(self, node):
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node.vhd = vhd_string()
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node.vhdOri = copy(node.vhd)
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@ -2255,16 +2327,16 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
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node.vhd = vhd_nat()
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node.vhdOri = copy(node.vhd)
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def visit_NameConstant(self, node):
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node.vhd = inferVhdlObj(node.value)
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node.vhdOri = copy(node.vhd)
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def visit_For(self, node):
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var = node.target.id
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# make it possible to detect loop variable
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self.tree.vardict[var] = _loopInt(-1)
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self.generic_visit(node)
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def visit_NameConstant(self, node):
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node.vhd = inferVhdlObj(node.value)
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node.vhdOri = copy(node.vhd)
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def visit_Name(self, node):
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if node.id in self.tree.vardict:
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node.obj = self.tree.vardict[node.id]
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@ -2391,6 +2463,9 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
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def accessIndex(self, node):
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self.generic_visit(node)
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node.vhd = vhd_std_logic() # XXX default
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if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
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node.slice.vhd = vhd_int()
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else:
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node.slice.value.vhd = vhd_int()
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obj = node.value.obj
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if isinstance(obj, list):
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@ -471,6 +471,7 @@ def _getSignString(s):
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else:
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return ''
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def _intRepr(n, radix=''):
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# write size for large integers (beyond 32 bits signed)
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# with some safety margin
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@ -478,11 +479,11 @@ def _intRepr(n, radix=''):
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p = abs(n)
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size = ''
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num = str(p).rstrip('L')
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if radix == "hex" or p >= 2**30:
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if radix == "hex" or p >= 2 ** 30:
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radix = "'h"
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num = hex(p)[2:].rstrip('L')
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if p >= 2**30:
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size = int(math.ceil(math.log(p+1,2))) + 1 # sign bit!
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if p >= 2 ** 30:
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size = int(math.ceil(math.log(p + 1, 2))) + 1 # sign bit!
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# if not radix:
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# radix = "'d"
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r = "%s%s%s" % (size, radix, num)
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@ -490,6 +491,7 @@ def _intRepr(n, radix=''):
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r = "(-%s)" % r
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return r
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def _convertGens(genlist, vfile):
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blockBuf = StringIO()
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funcBuf = StringIO()
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@ -750,7 +752,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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def visit_Assign(self, node):
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# shortcut for expansion of ROM in case statement
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if isinstance(node.value, ast.Subscript) and \
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isinstance(node.value.slice, ast.Index) and\
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not isinstance(node.value.slice, ast.Slice) and \
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isinstance(node.value.value.obj, _Rom):
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rom = node.value.value.obj.rom
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# self.write("// synthesis parallel_case full_case")
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@ -886,6 +888,32 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.write(")")
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self.context = None
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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if node.value is None:
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# NameConstant
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self.write(nameconstant_map[node.obj])
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elif isinstance(node.value, bool):
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self.write(nameconstant_map[node.obj])
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elif isinstance(node.value, int):
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# Num
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if self.context == _context.PRINT:
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self.write('"%s"' % node.value)
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else:
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self.write(self.IntRepr(node.value))
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elif isinstance(node.value, str):
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# Str
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s = node.value
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if self.context == _context.PRINT:
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self.write('"%s"' % s)
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elif len(s) == s.count('0') + s.count('1'):
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self.write("%s'b%s" % (len(s), s))
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else:
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self.write(s)
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else:
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def visit_Num(self, node):
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if self.context == _context.PRINT:
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self.write('"%s"' % node.n)
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@ -901,6 +929,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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else:
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self.write(s)
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def visit_NameConstant(self, node):
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self.write(nameconstant_map[node.obj])
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def visit_Continue(self, node):
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self.write("disable %s;" % self.labelStack[-1])
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@ -1074,9 +1105,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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def visit_ListComp(self, node):
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pass # do nothing
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def visit_NameConstant(self, node):
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self.write(nameconstant_map[node.obj])
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def visit_Name(self, node):
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if isinstance(node.ctx, ast.Store):
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self.setName(node)
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@ -1103,6 +1131,8 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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s = "1'b%s" % int(obj)
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elif isinstance(obj, int):
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s = self.IntRepr(obj)
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elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple
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s = n
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elif isinstance(obj, _Signal):
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addSignBit = isMixedExpr
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s = str(obj)
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@ -1115,7 +1145,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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elif (type(obj) in (type,)) and issubclass(obj, Exception):
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s = n
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else:
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self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj)))
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self.raiseError(node, _error.UnsupportedType, "%s, %s %s" % (n, type(obj), obj))
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else:
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raise AssertionError("name ref: %s" % n)
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if addSignBit:
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@ -1170,7 +1200,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.writeline()
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self.write("endcase")
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else:
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print (type(obj), type(a))
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self.write('$write("%s", ' % fs)
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self.visit(a)
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self.write(');')
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@ -1240,6 +1269,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.visit(node.value)
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self.write("[")
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# assert len(node.subs) == 1
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if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
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self.visit(node.slice)
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else:
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self.visit(node.slice.value)
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self.write("]")
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if addSignBit:
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||||
@ -1609,6 +1641,13 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
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return
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self.generic_visit(node)
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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node.signed = False
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else:
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def visit_Num(self, node):
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node.signed = False
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||||
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||||
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@ -2,15 +2,16 @@ import os
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path = os.path
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from random import randrange
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import myhdl
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from myhdl import *
|
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from myhdl.conversion import verify, analyze
|
||||
from myhdl import ConversionError
|
||||
from myhdl.conversion._misc import _error
|
||||
|
||||
|
||||
@block
|
||||
def ForLoopError1(a, out):
|
||||
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||||
@instance
|
||||
def logic():
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while 1:
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@ -20,10 +21,13 @@ def ForLoopError1(a, out):
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if a[i] == 1:
|
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var += 1
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out.next = var
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||||
|
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return logic
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||||
|
||||
|
||||
@block
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def ForLoopError2(a, out):
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@instance
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||||
def logic():
|
||||
while 1:
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@ -33,10 +37,13 @@ def ForLoopError2(a, out):
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if a[i] == 1:
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var += 1
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out.next = var
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return logic
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||||
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@block
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def ForLoop1(a, out):
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@instance
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def logic():
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while 1:
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@ -46,10 +53,13 @@ def ForLoop1(a, out):
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if a[i] == 1:
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var += 1
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out.next = var
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||||
|
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return logic
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||||
|
||||
|
||||
@block
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||||
def ForLoop2(a, out):
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||||
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@instance
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||||
def logic():
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||||
while 1:
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@ -59,10 +69,13 @@ def ForLoop2(a, out):
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if a[i] == 1:
|
||||
var += 1
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out.next = var
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||||
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||||
return logic
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||||
|
||||
|
||||
@block
|
||||
def ForLoop3(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
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||||
@ -72,10 +85,13 @@ def ForLoop3(a, out):
|
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if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
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||||
|
||||
return logic
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||||
|
||||
|
||||
@block
|
||||
def ForLoop4(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -85,10 +101,13 @@ def ForLoop4(a, out):
|
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if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def ForLoop5(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -98,10 +117,13 @@ def ForLoop5(a, out):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def ForLoop6(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -111,10 +133,13 @@ def ForLoop6(a, out):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def ForContinueLoop(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -125,10 +150,13 @@ def ForContinueLoop(a, out):
|
||||
continue
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def ForBreakLoop(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -138,10 +166,13 @@ def ForBreakLoop(a, out):
|
||||
if a[i] == 1:
|
||||
out.next = i
|
||||
break
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def ForBreakContinueLoop(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -152,10 +183,13 @@ def ForBreakContinueLoop(a, out):
|
||||
continue
|
||||
out.next = i
|
||||
break
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def NestedForLoop1(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -167,13 +201,16 @@ def NestedForLoop1(a, out):
|
||||
else:
|
||||
for j in downrange(i):
|
||||
if a[j] == 0:
|
||||
var +=1
|
||||
var += 1
|
||||
break
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def NestedForLoop2(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
@ -184,30 +221,36 @@ def NestedForLoop2(a, out):
|
||||
if a[i] == 0:
|
||||
continue
|
||||
else:
|
||||
for j in downrange(i-1):
|
||||
for j in downrange(i - 1):
|
||||
if a[j] == 0:
|
||||
pass
|
||||
else:
|
||||
out.next = j
|
||||
break
|
||||
break
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
def ReturnFromFunction(a):
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 1:
|
||||
return i
|
||||
return 0
|
||||
|
||||
|
||||
@block
|
||||
def FunctionCall(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
yield a
|
||||
out.next = ReturnFromFunction(a)
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
# During the following check, I noticed that non-blocking assignments
|
||||
# are not scheduled when a task is disabled in Icarus. Apparently
|
||||
# this is one of the many vague areas in the Verilog standard.
|
||||
@ -218,8 +261,10 @@ def ReturnFromTask(a, out):
|
||||
return
|
||||
out[:] = 23 # to notice it
|
||||
|
||||
|
||||
@block
|
||||
def TaskCall(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
var = intbv(0)[8:]
|
||||
@ -227,31 +272,37 @@ def TaskCall(a, out):
|
||||
yield a
|
||||
ReturnFromTask(a, var)
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def WhileLoop(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
i = len(a) - 1
|
||||
while i >= 0:
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
i -= 1
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def WhileContinueLoop(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
i = len(a) - 1
|
||||
while i >= 0:
|
||||
if a[i] == 0:
|
||||
i -= 1
|
||||
@ -259,32 +310,38 @@ def WhileContinueLoop(a, out):
|
||||
var += 1
|
||||
i -= 1
|
||||
out.next = var
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def WhileBreakLoop(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
i = len(a) - 1
|
||||
out.next = 0
|
||||
while i >= 0:
|
||||
if a[i] == 1:
|
||||
out.next = i
|
||||
break
|
||||
i -= 1
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def WhileBreakContinueLoop(a, out):
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
i = len(a) - 1
|
||||
out.next = 0
|
||||
while i >= 0:
|
||||
if a[i] == 0:
|
||||
@ -292,8 +349,10 @@ def WhileBreakContinueLoop(a, out):
|
||||
continue
|
||||
out.next = i
|
||||
break
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
@block
|
||||
def LoopBench(LoopTest):
|
||||
|
||||
@ -301,7 +360,7 @@ def LoopBench(LoopTest):
|
||||
z = Signal(intbv(0)[16:])
|
||||
|
||||
looptest_inst = LoopTest(a, z)
|
||||
data = tuple([randrange(2**min(i, 16)) for i in range(100)])
|
||||
data = tuple([randrange(2 ** min(i, 16)) for i in range(100)])
|
||||
|
||||
@instance
|
||||
def stimulus():
|
||||
@ -321,6 +380,7 @@ def testForLoopError1():
|
||||
else:
|
||||
assert False
|
||||
|
||||
|
||||
def testForLoopError2():
|
||||
try:
|
||||
analyze(LoopBench(ForLoopError2))
|
||||
@ -329,47 +389,64 @@ def testForLoopError2():
|
||||
else:
|
||||
assert False
|
||||
|
||||
|
||||
def testForLoop1():
|
||||
assert verify(LoopBench(ForLoop1)) == 0
|
||||
|
||||
|
||||
def testForLoop2():
|
||||
assert verify(LoopBench(ForLoop2)) == 0
|
||||
|
||||
|
||||
def testForLoop4():
|
||||
assert verify(LoopBench(ForLoop4)) == 0
|
||||
|
||||
|
||||
def testForLoop5():
|
||||
assert verify(LoopBench(ForLoop5)) == 0
|
||||
|
||||
# for loop 3 and 6 can't work in vhdl
|
||||
|
||||
|
||||
def testForContinueLoop():
|
||||
assert verify(LoopBench(ForContinueLoop)) == 0
|
||||
|
||||
|
||||
def testForBreakLoop():
|
||||
assert verify(LoopBench(ForBreakLoop)) == 0
|
||||
|
||||
|
||||
def testForBreakContinueLoop():
|
||||
assert verify(LoopBench(ForBreakContinueLoop))== 0
|
||||
assert verify(LoopBench(ForBreakContinueLoop)) == 0
|
||||
|
||||
|
||||
def testNestedForLoop1():
|
||||
assert verify(LoopBench(NestedForLoop1)) == 0
|
||||
|
||||
|
||||
def testNestedForLoop2():
|
||||
assert verify(LoopBench(NestedForLoop2)) == 0
|
||||
|
||||
def testWhileLoop():
|
||||
|
||||
def testFunctionCall():
|
||||
assert verify(LoopBench(FunctionCall)) == 0
|
||||
|
||||
## def testTaskCall(self):
|
||||
## sim = self.bench(TaskCall)
|
||||
## Simulation(sim).run()
|
||||
# # def testTaskCall(self):
|
||||
# # sim = self.bench(TaskCall)
|
||||
# # Simulation(sim).run()
|
||||
|
||||
|
||||
def testWhileLoop():
|
||||
assert verify(LoopBench(WhileLoop)) == 0
|
||||
|
||||
|
||||
def testWhileContinueLoop():
|
||||
assert verify(LoopBench(WhileContinueLoop)) == 0
|
||||
|
||||
|
||||
def testWhileBreakLoop():
|
||||
assert verify(LoopBench(WhileBreakLoop)) == 0
|
||||
|
||||
|
||||
def testWhileBreakContinueLoop():
|
||||
assert verify(LoopBench(WhileBreakContinueLoop)) == 0
|
||||
|
||||
@ -3,8 +3,7 @@ path = os.path
|
||||
import unittest
|
||||
from unittest import TestCase
|
||||
|
||||
import myhdl
|
||||
from myhdl import *
|
||||
from myhdl import enum, block, Signal, intbv, always, instance, delay, StopSimulation
|
||||
|
||||
from .util import setupCosimulation
|
||||
|
||||
@ -15,6 +14,7 @@ t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC')
|
||||
t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
|
||||
t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold")
|
||||
|
||||
|
||||
@block
|
||||
def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
|
||||
|
||||
@ -53,12 +53,13 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
|
||||
if index == 0:
|
||||
if not syncFlag:
|
||||
state.next = t_State.SEARCH
|
||||
SOF.next = (index == FRAME_SIZE-1)
|
||||
SOF.next = (index == FRAME_SIZE - 1)
|
||||
else:
|
||||
raise ValueError("Undefined state")
|
||||
|
||||
return FSM
|
||||
|
||||
|
||||
@block
|
||||
def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
|
||||
|
||||
@ -72,7 +73,6 @@ def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
|
||||
|
||||
"""
|
||||
|
||||
|
||||
@instance
|
||||
def FSM():
|
||||
index = intbv(0)[8:] # position in frame
|
||||
@ -100,15 +100,16 @@ def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
|
||||
if index == 0:
|
||||
if not syncFlag:
|
||||
state_var = t_State.SEARCH
|
||||
SOF_var = (index == FRAME_SIZE-1)
|
||||
SOF_var = (index == FRAME_SIZE - 1)
|
||||
else:
|
||||
raise ValueError("Undefined state")
|
||||
index[:]= (index + 1) % FRAME_SIZE
|
||||
index[:] = (index + 1) % FRAME_SIZE
|
||||
SOF.next = SOF_var
|
||||
state.next = state_var
|
||||
|
||||
return FSM
|
||||
|
||||
|
||||
@block
|
||||
def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
|
||||
|
||||
@ -147,10 +148,10 @@ def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
|
||||
if index == 0:
|
||||
if not syncFlag:
|
||||
state.next = t_State.SEARCH
|
||||
SOF.next = (index == FRAME_SIZE-1)
|
||||
SOF.next = (index == FRAME_SIZE - 1)
|
||||
else:
|
||||
raise ValueError("Undefined state")
|
||||
index[:]= (index + 1) % FRAME_SIZE
|
||||
index[:] = (index + 1) % FRAME_SIZE
|
||||
|
||||
return logic
|
||||
|
||||
@ -192,13 +193,13 @@ class FramerCtrlTest(TestCase):
|
||||
|
||||
@instance
|
||||
def stimulus():
|
||||
for i in range(3):
|
||||
for __ in range(3):
|
||||
yield clk.posedge
|
||||
for n in (12, 8, 8, 4, 11, 8, 8, 7, 6, 8, 8):
|
||||
syncFlag.next = 1
|
||||
yield clk.posedge
|
||||
syncFlag.next = 0
|
||||
for i in range(n-1):
|
||||
for __ in range(n - 1):
|
||||
yield clk.posedge
|
||||
raise StopSimulation
|
||||
|
||||
@ -213,7 +214,6 @@ class FramerCtrlTest(TestCase):
|
||||
|
||||
return framerctrl_ref_inst, framerctrl_v_inst, clkgen, stimulus, check
|
||||
|
||||
|
||||
def testRef(self):
|
||||
for t_State in (t_State_b, t_State_oc, t_State_oh):
|
||||
tb_fsm = self.bench(FramerCtrl_ref, t_State)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user