FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

Modified bit inversion operation according to newsgroup discussion.

Browse Source 
Added support for bit inversion on signed vars in Verilog
and VHDL conversion
This commit is contained in:
jand 2008-03-09 14:22:25 +00:00
parent b1e3b1a1f7
commit 7c4189fd42
5 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
myhdl/_intbv.py
View File

@ -402,7 +402,7 @@ class intbv(object):
return abs(self._val)
def __invert__(self):
if self._nrbits:
if self._nrbits and self._min >= 0:
return intbv(~self._val & (1L << self._nrbits)-1)
else:
return intbv(~self._val)

2
myhdl/conversion/_toVHDL.py
View File

@ -573,7 +573,7 @@ class _ConvertVisitor(_ConversionMixin):
self.shiftOp(node, "shift_right")
def checkOpWithNegIntbv(self, node, op):
if op in ("+", "-", "*", "&&", "||", "!"):
if op in ("+", "-", "not ", "*", "&&", "||", "!"):
return
if isinstance(node, astNode.Name):
o = node.obj

2
myhdl/conversion/_toVerilog.py
View File

@ -416,7 +416,7 @@ class _ConvertVisitor(_ConversionMixin):
self.binaryOp(node, '>>>')
def checkOpWithNegIntbv(self, node, op):
if op in ("+", "-", "*", "&&", "||", "!"):
if op in ("+", "-", "*", "~", "&&", "||", "!"):
return
if isinstance(node, astNode.Name):
o = node.obj

4
myhdl/test/toVHDL/test_signed.py
View File

@ -206,7 +206,7 @@ def unaryOps(
while 1:
yield arg
# BoolNot.next = not arg
# Invert.next = ~arg
Invert.next = ~arg
# UnaryAdd.next = +arg
UnarySub.next = --arg
@ -245,7 +245,7 @@ def unaryBench( m):
yield arg
yield delay(1)
# print BoolNot
# print Invert
print Invert
# print UnaryAdd
print UnarySub

4
myhdl/test/toVerilog/test_signed.py
View File

@ -250,7 +250,7 @@ def unaryOps(
while 1:
yield arg
Not.next = not arg
# Invert.next = ~arg
Invert.next = ~arg
UnaryAdd.next = +arg
UnarySub.next = --arg
@ -307,7 +307,7 @@ class TestUnaryOps(TestCase):
yield arg
yield delay(1)
self.assertEqual(Not, Not_v)
#self.assertEqual(Invert, Invert_v)
self.assertEqual(Invert, Invert_v)
self.assertEqual(UnaryAdd, UnaryAdd_v)
self.assertEqual(UnarySub, UnarySub_v)