named and positional args

myhdl/_toVerilog/__init__.py

@@ -56,6 +56,7 @@ _error.ReturnIntbvBitWidth = "Returned intbv instance should have bit width"
 _error.ReturnTypeInfer = "Can't infer return type"
 _error.ShadowingSignal = "Port is shadowed by internal signal"
 _error.FreeVarTypeError = "Free variable should be a Signal or an int"
+_error.ExtraArguments = "Extra positional or named arguments are not supported"
 
 
 _access = enum("INPUT", "OUTPUT", "INOUT", "UNKNOWN")

myhdl/_toVerilog/_analyze.py

@@ -172,6 +172,10 @@ class _NotSupportedVisitor(_ToVerilogMixin):
         self.visit(node.expr, *args)
         
     def visitCallFunc(self, node, context=_context.UNKNOWN):
+        if node.star_args:
+            self.raiseError(node, _error.NotSupported, "extra positional arguments")
+        if node.dstar_args:
+            self.raiseError(node, _error.NotSupported, "extra named arguments")
         f = eval(_unparse(node.node), self.ast.symdict)
         if f is bool:
             context = _context.BOOLEAN
@@ -183,6 +187,8 @@ class _NotSupportedVisitor(_ToVerilogMixin):
         self.visitChildNodes(node, *args)
         
     def visitFunction(self, node, *args):
+        if node.flags != 0: # check flags
+            self.raiseError(node, _error.NotSupported, "extra positional or named arguments")
         if not self.toplevel:
             self.raiseError(node, _error.NotSupported, "embedded function definition")
         self.toplevel = False
@@ -653,8 +659,8 @@ class _AnalyzeTopFuncVisitor(object):
         self.argdict = {}
     
     def visitFunction(self, node):
-        if node.flags != 0: # check flags
-            raise AssertionError("unsupported function type")
+ ##        if node.flags != 0: # check flags
+##             raise AssertionError("unsupported function type")
         self.name = node.name
         argnames = node.argnames
         i=-1

myhdl/test/toVerilog/test_NotSupported.py

@@ -249,18 +249,58 @@ class TestNotSupported(unittest.TestCase):
                 else:
                     z.next = a < (b or c)
         self.check(g, z, a, b)
-    
+
+    def testExtraArguments(self):
+        a, b, c = [Signal(bool()) for i in range(3)]
+        c = [1, 2]
+        def g(a, *args):
+            yield a
+        def f(a, b, c, *args):
+            return g(a, b)
+        self.check(f, a, b, c)
+
+    def testExtraPositionalArgsInCall(self):
+        a, b, c = [Signal(bool()) for i in range(3)]
+        c = [1]
+        d = {'b':2}
+        def h(b):
+            return b
+        def g(a):
+            h(*c)
+            yield a
+        def f(a, b, c):
+            return g(a)
+        x = self.check(f, a, b, c)
+        
+    def testExtraNamedArgsInCall(self):
+        a, b, c = [Signal(bool()) for i in range(3)]
+        c = [1]
+        d = {'b':2}
+        def h(b):
+            return b
+        def g(a):
+            h(**d)
+            yield a
+        def f(a, b, c):
+            return g(a)
+        x = self.check(f, a, b, c)
+   
 
 
 class TestMisc(unittest.TestCase):
     def test(self):
         a, b, c = [Signal(bool()) for i in range(3)]
-        c = [1, 2]
-        def g(a, b, c):
-            yield a 
-            a.next = b is c
-        x = g(a, b, c)
-        x = toVerilog(g,a, b, c)
+        c = [1]
+        d = {'a':2}
+        def h(b):
+            return b
+        def g(a):
+            h(a)
+            yield a
+        def f(a, b, c):
+            return g(a)
+        f(a, b, c)
+        x = toVerilog(f, a, b, c)