diff --git a/CHANGES.txt b/CHANGES.txt
index 68297287..67d6108b 100644
--- a/CHANGES.txt
+++ b/CHANGES.txt
@@ -1,4 +1,4 @@
-Release 0.9.0 7-Jul-2015 
+Release 0.9.0 11-Jul-2015 
 -------------------------
 
 Full details about new features and changes can be found here:
diff --git a/doc/source/conf.py b/doc/source/conf.py
index ff3782ef..2c5674ff 100644
--- a/doc/source/conf.py
+++ b/doc/source/conf.py
@@ -44,7 +44,7 @@ master_doc = 'index'
 
 # General information about the project.
 project = u'MyHDL'
-copyright = u'2014, Jan Decaluwe'
+copyright = u'2015, Jan Decaluwe'
 
 # The version info for the project you're documenting, acts as replacement for
 # |version| and |release|, also used in various other places throughout the
diff --git a/doc/source/whatsnew/0.4.rst b/doc/source/whatsnew/0.4.rst
index 9967f03a..933fa4ec 100644
--- a/doc/source/whatsnew/0.4.rst
+++ b/doc/source/whatsnew/0.4.rst
@@ -1,6 +1,6 @@
-=======================================
-New in MyHDL 0.4: Conversion to Verilog
-=======================================
+==============================================
+What's new in MyHDL 0.4: Conversion to Verilog
+==============================================
 
 :Author: Jan Decaluwe
 
diff --git a/doc/source/whatsnew/0.9.rst b/doc/source/whatsnew/0.9.rst
index 5655b578..ed7e7a87 100644
--- a/doc/source/whatsnew/0.9.rst
+++ b/doc/source/whatsnew/0.9.rst
@@ -6,9 +6,12 @@
 What's new in MyHDL 0.9
 ***********************
 
-Python 3 Support
+Python 3 support
 ================
-Experimental Python 3 support has been added to MyHDL 0.9
+
+Experimental Python 3 support has been added to MyHDL 0.9.
+This was a major effort to modernize the code. As a result,
+Python 2 and 3 are supported from a single codebase.
 
 See :doc:`/python3` for more info.
 
@@ -71,3 +74,41 @@ For additional information see the original proposal `mep-107`_.
 
 .. _mep-107: http://dev.myhdl.org/meps/mep-107.html
 .. _MyHDL generator: http://docs.myhdl.org/en/latest/manual/reference.html#myhdl-generators-and-trigger-objects
+
+Other noteworthy improvements
+=============================
+
+``ConcatSignal`` interface
+--------------------------
+
+The interface of :class:`ConcatSignal` was enhanced. In
+addition to signals, you can now also use constant values 
+in the concatenation.
+
+``std_logic`` type ports 
+------------------------
+
+:func:`toVHDL` has a new attibute ``std_logic_ports``. When
+set, only ``std_logic`` type ports are used in the interface
+of the top-level VHDL module.
+
+Development flow
+----------------
+
+The MyHDL development flow has been modernized by moving to git and `github`_
+for version control. In addition, travis has set up so that all pull requests
+are tested automatically, enabling continuous intergration.
+
+Acknowledgments
+===============
+
+The Python 3 support effort was coordinated by Keerthan Jaic, who also
+implemented most of if. Convertible interfaces were championed by Chris Felton,
+and implemented by Keerthan Jaic.
+
+MyHDL development is a collaborative effort, as can be seen on `github`_.
+Thanks to all who contributed with suggestions, issues and pull requests.
+
+.. _github: https://www.github.com/jandecaluwe/myhdl
+
+