FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

Fixed _VHDLNameValidation.py method calls in _toVHDL.py

Browse Source
This commit is contained in:
Patrick Egan 2016-09-01 23:57:03 -04:00
parent e11125a07a
commit 7f31b570f7
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
myhdl/conversion/_toVHDL.py
View File

@ -354,7 +354,7 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor
if convertPort:
pt = "std_logic_vector"
# Check if VHDL keyword or reused name
_nameCheck._nameValid(s)
_VHDLNameValidation._nameValid(s)
if s._driven:
if s._read:
if not isinstance(s, _TristateSignal):
@ -419,7 +419,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
print("signal %s: %s%s;" % (s._name, p, r), file=f)
elif s._read:
# Check if VHDL keyword or reused name
_nameCheck._nameValid(s)
_VHDLNameValidation._nameValid(s)
# the original exception
# raise ToVHDLError(_error.UndrivenSignal, s._name)
# changed to a warning and a continuous assignment to a wire
@ -440,7 +440,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
if not m._driven and not m._read:
continue
# Check if VHDL keyword or reused name
_nameCheck._nameValid(m)
_VHDLNameValidation._nameValid(m)
r = _getRangeString(m.elObj)
p = _getTypeString(m.elObj)
t = "t_array_%s" % m.name