diff --git a/myhdl/_Cosimulation.py b/myhdl/_Cosimulation.py
index c65114d0..2919ad85 100644
--- a/myhdl/_Cosimulation.py
+++ b/myhdl/_Cosimulation.py
@@ -136,8 +136,7 @@ class Cosimulation(object):
             s, v = self._toSigDict[e[i]], e[i+1]
             try:
                 next = int(v, 16)
-                # signed support
-                if (s._type is intbv) and (s._min < 0):
+                if s._nrbits and s._min is not None and s._min < 0:
                     if next >= (1 << (s._nrbits-1)):
                         next -= (1 << s._nrbits)
             except ValueError:
@@ -154,7 +153,11 @@ class Cosimulation(object):
         if self._hasChange:
             self._hasChange = 0
             for s in self._fromSigs:
-                buf = hex(s)[2:]
+                v = int(s._val)
+                # signed support
+                if s._nrbits and v < 0:
+                    v += (1 << s._nrbits)
+                buf = hex(v)[2:]
                 if buf[-1] == 'L':
                     buf = buf[:-1] # strip trailing L
                 buflist.append(buf)
diff --git a/myhdl/__init__.py b/myhdl/__init__.py
index 38bd1917..94b0b893 100644
--- a/myhdl/__init__.py
+++ b/myhdl/__init__.py
@@ -48,7 +48,7 @@ __author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
 __revision__ = "$Revision$"
 __date__ = "$Date$"
 
-__version__ = "0.4.2-dev"
+__version__ = "0.5dev1"
 
 import warnings
 
diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py
index f5935434..57ec75cf 100644
--- a/myhdl/_intbv.py
+++ b/myhdl/_intbv.py
@@ -36,7 +36,7 @@ from __builtin__ import max as maxfunc
 class intbv(object):
     __slots__ = ('_val', '_min', '_max', '_nrbits')
     
-    def __init__(self, val=0, min=None, max=None, _nrbits=0):
+    def __init__(self, val=None, min=None, max=None, _nrbits=0):
         if _nrbits:
             self._min = 0
             self._max = 2**_nrbits
@@ -45,6 +45,13 @@ class intbv(object):
             self._max = max
             if max is not None and min is not None:
                 _nrbits = maxfunc(len(bin(max-1)), len(bin(min)))
+                if min >= 0:
+                    _nrbits = len(bin(max-1))
+                elif max <= 0:
+                    _nrbits = len(bin(min))
+                else:
+                    # make sure there is a leading zero bit in positive numbers
+                    _nrbits = maxfunc(len(bin(max-1))+1, len(bin(min)))
         if isinstance(val, (int, long)):
             self._val = val
         elif isinstance(val, StringType):
@@ -114,6 +121,8 @@ class intbv(object):
     def __getitem__(self, key):
         if isinstance(key, int):
             i = key
+            if self._val is None:
+                return intbv(None, _nrbits=1)
             res = intbv((self._val >> i) & 0x1, _nrbits=1)
             return res
         elif isinstance(key, slice):
@@ -128,6 +137,8 @@ class intbv(object):
             if i <= j:
                 raise ValueError, "intbv[i:j] requires i > j\n" \
                       "            i, j == %s, %s" % (i, j)
+            if self._val is None:
+                return intbv(None, _nrbits=i-j)
             res = intbv((self._val & (1L << i)-1) >> j, _nrbits=i-j)
             return res
         else:
@@ -147,6 +158,8 @@ class intbv(object):
         elif isinstance(key, slice):
             i, j = key.start, key.stop
             if j is None: # default
+                if i is None and self._val is None:
+                    self._val = val
                 j = 0
             if j < 0:
                 raise ValueError, "intbv[i:j] = v requires j >= 0\n" \
diff --git a/myhdl/_toVerilog/_analyze.py b/myhdl/_toVerilog/_analyze.py
index 9f8e3673..143a16cb 100644
--- a/myhdl/_toVerilog/_analyze.py
+++ b/myhdl/_toVerilog/_analyze.py
@@ -45,7 +45,10 @@ from myhdl._extractHierarchy import _isMem
 
 myhdlObjects = myhdl.__dict__.values()
 builtinObjects = __builtin__.__dict__.values()
- 
+
+_signed = False
+def _isSigned():
+    return _signed
 
 def _makeName(n, prefixes):
     if len(prefixes) > 1:
@@ -59,6 +62,7 @@ def _makeName(n, prefixes):
     return name
                     
 def _analyzeSigs(hierarchy):
+    global _signed
     curlevel = 0
     siglist = []
     memlist = []
@@ -79,6 +83,8 @@ def _analyzeSigs(hierarchy):
         for n, s in sigdict.items():
             if s._name is not None:
                 continue
+            if s._min is not None and s._min < 0:
+                _signed = True
             s._name = _makeName(n, prefixes)
             if not s._nrbits:
                 raise ToVerilogError(_error.UndefinedBitWidth, s._name)
@@ -107,6 +113,8 @@ def _analyzeSigs(hierarchy):
                 raise ToVerilogError(_error.InconsistentType, s._name)
             if s._nrbits != m.elObj._nrbits:
                 raise ToVerilogError(_error.InconsistentBitWidth, s._name)
+            if s._min is not None and s._min < 0:
+                _signed = True
             
     return siglist, memlist
 
@@ -378,6 +386,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
         self.visit(node.expr, _access.OUTPUT)
         
     def visitAssign(self, node, access=_access.OUTPUT, *args):
+        global _signed
         target, expr = node.nodes[0], node.expr
         self.visit(target, _access.OUTPUT)
         if isinstance(target, astNode.AssName):
@@ -392,6 +401,8 @@ class _AnalyzeVisitor(_ToVerilogMixin):
                     self.raiseError(node, _error.IntbvBitWidth, n)
 ##                 if obj._min < 0:
 ##                     self.raiseError(node, _error.IntbvSign, n)
+                    if obj._min < 0:
+                        _signed = True
             if n in self.ast.vardict:
                 curObj = self.ast.vardict[n]
                 if isinstance(obj, type(curObj)):
diff --git a/myhdl/_toVerilog/_convert.py b/myhdl/_toVerilog/_convert.py
index 5672a129..05e70d2d 100644
--- a/myhdl/_toVerilog/_convert.py
+++ b/myhdl/_toVerilog/_convert.py
@@ -44,7 +44,7 @@ from myhdl._always_comb import _AlwaysComb
 from myhdl._toVerilog import _error, _access, _kind,_context, \
      _ToVerilogMixin, _Label
 from myhdl._toVerilog._analyze import _analyzeSigs, _analyzeGens, _analyzeTopFunc, \
-     _Ram, _Rom
+     _Ram, _Rom, _isSigned
             
 _converting = 0
 _profileFunc = None
@@ -134,13 +134,13 @@ def _writeModuleHeader(f, intf):
         r = _getRangeString(s)
         p = _getSignString(s)
         if s._driven:
-            print >> f, "output %s%s;" % (r, portname)
+            print >> f, "output %s%s%s;" % (p, r, portname)
             if s._driven == 'reg':
                 print >> f, "reg %s%s%s;" % (p, r, portname)
             else:
-                print >> f, "wire %s%s;" % (r, portname)
+                print >> f, "wire %s%s%s;" % (p, r, portname)
         else:
-            print >> f, "input %s%s;" % (r, portname)
+            print >> f, "input %s%s%s;" % (p, r, portname)
     print >> f
 
 
@@ -218,12 +218,17 @@ def _getRangeString(s):
     if s._type is bool:
         return ''
     elif s._nrbits is not None:
-        return "[%s:0] " % (s._nrbits-1)
+        nrbits = s._nrbits
+        if _isSigned():
+            # add a sign bit to positive numbers
+            if s._type is intbv and s._min >=0:
+                nrbits += 1
+        return "[%s:0] " % (nrbits-1)
     else:
         raise AssertionError
 
 def _getSignString(s):
-    if (s._type is intbv) and (s._min < 0):
+    if _isSigned() and s._type is intbv:
         return "signed "
     else:
         return ''
@@ -282,7 +287,9 @@ class _ConvertVisitor(_ToVerilogMixin):
         else:
             raise AssertionError("var %s has unexpected type %s" % (name, type(obj)))
         # initialize regs
-        if dir == 'reg ' and not isinstance(obj, _Ram):
+        # if dir == 'reg ' and not isinstance(obj, _Ram):
+        # disable for cver
+        if False:
             if str(type(obj)) == "<class 'myhdl._enum.EnumItem'>":
                 inival = obj._toVerilog()
             else:
diff --git a/myhdl/test/test_inferWaiter.py b/myhdl/test/test_inferWaiter.py
index 34ec7a70..bdf7bd51 100644
--- a/myhdl/test/test_inferWaiter.py
+++ b/myhdl/test/test_inferWaiter.py
@@ -107,7 +107,7 @@ class InferWaiterTest(TestCase):
 
     def bench(self, genFunc, waiterType):
 
-        a, b, c, d, r, s = [Signal(intbv()) for i in range(6)]
+        a, b, c, d, r, s = [Signal(intbv(0)) for i in range(6)]
 
         gen_inst_r = genFunc(a, b, c, d, r)
         self.assertEqual(type(_inferWaiter(gen_inst_r)), waiterType)
diff --git a/myhdl/test/test_intbv.py b/myhdl/test/test_intbv.py
index c2e9b159..22ee043d 100644
--- a/myhdl/test/test_intbv.py
+++ b/myhdl/test/test_intbv.py
@@ -37,7 +37,7 @@ from myhdl._intbv import intbv
 
 class TestIntbvInit(TestCase):
     def testDefaultValue(self):
-        self.assertEqual(intbv(), 0)
+        self.assertEqual(intbv(), None)
     
 
 def getItem(s, i):
diff --git a/myhdl/test/toVerilog/test_GrayInc.py b/myhdl/test/toVerilog/test_GrayInc.py
index f741eb4f..34ad68d9 100644
--- a/myhdl/test/toVerilog/test_GrayInc.py
+++ b/myhdl/test/toVerilog/test_GrayInc.py
@@ -14,7 +14,7 @@ ACTIVE_LOW, INACTIVE_HIGH = 0, 1
 
 def GrayInc(graycnt, enable, clock, reset, width):
     
-    bincnt = Signal(intbv()[width:])
+    bincnt = Signal(intbv(0)[width:])
     
     INC_1 = inc(bincnt, enable, clock, reset, n=2**width)
     BIN2GRAY_1 = bin2gray(B=bincnt, G=graycnt, width=width)
@@ -24,7 +24,7 @@ def GrayInc(graycnt, enable, clock, reset, width):
 
 def GrayIncReg(graycnt, enable, clock, reset, width):
     
-    graycnt_comb = Signal(intbv()[width:])
+    graycnt_comb = Signal(intbv(0)[width:])
     
     GRAY_INC_1 = GrayInc(graycnt_comb, enable, clock, reset, width)
     
@@ -38,14 +38,14 @@ def GrayIncReg(graycnt, enable, clock, reset, width):
 
 
 width = 8
-graycnt = Signal(intbv()[width:])
+graycnt = Signal(intbv(0)[width:])
 enable, clock, reset = [Signal(bool()) for i in range(3)]
 # GrayIncReg(graycnt, enable, clock, reset, width)
 
 def GrayIncReg_v(name, graycnt, enable, clock, reset, width):
     return setupCosimulation(**locals())
 
-graycnt_v = Signal(intbv()[width:])
+graycnt_v = Signal(intbv(0)[width:])
 
 class TestGrayInc(unittest.TestCase):
 
diff --git a/myhdl/test/toVerilog/test_RandomScrambler.py b/myhdl/test/toVerilog/test_RandomScrambler.py
index f2ec0e47..02a4ea12 100644
--- a/myhdl/test/toVerilog/test_RandomScrambler.py
+++ b/myhdl/test/toVerilog/test_RandomScrambler.py
@@ -5,6 +5,7 @@ from unittest import TestCase
 import random
 from random import randrange
 random.seed(2)
+import time
 
 from myhdl import *
 
@@ -83,9 +84,9 @@ def RandomScrambler_v(name,
 class TestRandomScrambler(TestCase):
 
     def stimulus(self):
-        input = intbv()
-        output = intbv()
-        output_v = intbv()
+        input = intbv(0)
+        output = intbv(0)
+        output_v = intbv(0)
         for i in range(100):
         # while 1:
             input[:] = randrange(M)
@@ -119,11 +120,13 @@ class TestRandomScrambler(TestCase):
 ##             print input
             self.assertEqual(output, output_v)
 
+            
     def test(self):
         rs = toVerilog(RandomScrambler, 
                        o7, o6, o5, o4, o3, o2, o1, o0,
                        i7, i6, i5, i4, i3, i2, i1, i0
                        )
+        # time.sleep(1)
         rs_v = RandomScrambler_v(RandomScrambler.func_name,
                                  v7, v6, v5, v4, v3, v2, v1, v0,
                                  i7, i6, i5, i4, i3, i2, i1, i0
diff --git a/myhdl/test/toVerilog/test_dec.py b/myhdl/test/toVerilog/test_dec.py
new file mode 100644
index 00000000..5460e332
--- /dev/null
+++ b/myhdl/test/toVerilog/test_dec.py
@@ -0,0 +1,200 @@
+import os
+path = os.path
+import unittest
+from unittest import TestCase
+import random
+from random import randrange
+random.seed(2)
+
+from myhdl import *
+
+from util import setupCosimulation
+
+ACTIVE_LOW, INACTIVE_HIGH = 0, 1
+
+def decRef(count, enable, clock, reset, n):
+    """ Decrementer with enable.
+    
+    count -- output
+    enable -- control input, decrement when 1
+    clock -- clock input
+    reset -- asynchronous reset input
+    n -- counter max value
+    """
+    while 1:
+        yield posedge(clock), negedge(reset)
+        if reset == ACTIVE_LOW:
+            count.next = 0
+        else:
+            if enable:
+                if count == -n:
+                    count.next = n-1
+                else:
+                    count.next = count - 1
+                
+def dec(count, enable, clock, reset, n):
+    """ Decrementer with enable.
+    
+    count -- output
+    enable -- control input, decrement when 1
+    clock -- clock input
+    reset -- asynchronous reset input
+    n -- counter max value
+    """
+    def decProcess():
+        while 1:
+            yield posedge(clock), negedge(reset)
+            if reset == ACTIVE_LOW:
+                count.next = 0
+            else:
+                if enable:
+                    if count == -n:
+                        count.next = n-1
+                    else:
+                        count.next = count - 1
+    return decProcess()
+
+def decTask(count, enable, clock, reset, n):
+    
+    def decTaskFunc(cnt, enable, reset, n):
+        if enable:
+            if cnt == -n:
+                cnt.next = n-1
+            else:
+                cnt.next = cnt - 1
+ 
+    def decTaskGen():
+        cnt = intbv(0, min=-n, max=n)
+        while 1:
+            yield posedge(clock), negedge(reset)
+            if reset == ACTIVE_LOW:
+                cnt[:] = 0
+                count.next = 0
+            else:
+                # print count
+                decTaskFunc(cnt, enable, reset, n)
+                count.next = cnt
+
+    return decTaskGen()
+
+
+def decTaskFreeVar(count, enable, clock, reset, n):
+    
+    def decTaskFunc():
+        if enable:
+            if count == -n:
+                count.next = n-1
+            else:
+                count.next = count - 1
+ 
+    def decTaskGen():
+        while 1:
+            yield posedge(clock), negedge(reset)
+            if reset == ACTIVE_LOW:
+               count.next = 0
+            else:
+                # print count
+                decTaskFunc()
+
+    return decTaskGen()
+
+
+      
+def dec_v(name, count, enable, clock, reset):
+    return setupCosimulation(**locals())
+
+class TestDec(TestCase):
+
+    def clockGen(self, clock):
+        while 1:
+            yield delay(10)
+            clock.next = not clock
+    
+    def stimulus(self, enable, clock, reset):
+        reset.next = INACTIVE_HIGH
+        yield negedge(clock)
+        reset.next = ACTIVE_LOW
+        yield negedge(clock)
+        reset.next = INACTIVE_HIGH
+        for i in range(1000):
+            enable.next = 1
+            yield negedge(clock)
+        for i in range(1000):
+            enable.next = min(1, randrange(5))
+            yield negedge(clock)
+        raise StopSimulation
+
+    def check(self, count, count_v, enable, clock, reset, n):
+        expect = 0
+        yield posedge(reset)
+        self.assertEqual(count, expect)
+        self.assertEqual(count, count_v)
+        while 1:
+            yield posedge(clock)
+            if enable:
+                if expect == -n:
+                    expect = n-1
+                else:
+                    expect -= 1
+            yield delay(1)
+            # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
+            self.assertEqual(count, expect)
+            self.assertEqual(count, count_v)
+                
+    def bench(self, dec):
+
+        m = 8
+        n = 2 ** (m-1)
+  
+        count = Signal(intbv(0, min=-n, max=n))
+        count_v = Signal(intbv(0, min=-n, max=n))
+        enable = Signal(bool(0))
+        clock, reset = [Signal(bool()) for i in range(2)]
+
+        dec_inst_ref = decRef(count, enable, clock, reset, n=n)
+        dec_inst = toVerilog(dec, count, enable, clock, reset, n=n)
+        # dec_inst = dec(count, enable, clock, reset, n=n)
+        dec_inst_v = dec_v(dec.func_name, count_v, enable, clock, reset)
+        clk_1 = self.clockGen(clock)
+        st_1 = self.stimulus(enable, clock, reset)
+        ch_1 = self.check(count, count_v, enable, clock, reset, n=n)
+
+        sim = Simulation(dec_inst_ref, dec_inst_v, clk_1, st_1, ch_1)
+        return sim
+
+    def testDecRef(self):
+        """ Check decrement operation """
+        sim = self.bench(decRef)
+        sim.run(quiet=1)
+        
+    def testDec(self):
+        """ Check decrement operation """
+        sim = self.bench(dec)
+        sim.run(quiet=1)
+
+## signed inout in task doesn't work yet in Icarus
+##     def testDecTask(self):
+##         sim = self.bench(decTask)
+##         sim.run(quiet=1)
+        
+    def testDecTaskFreeVar(self):
+        sim = self.bench(decTaskFreeVar)
+        sim.run(quiet=1)
+
+if __name__ == '__main__':
+    unittest.main()
+
+
+            
+            
+
+    
+
+    
+        
+
+
+                
+
+        
+
diff --git a/myhdl/test/toVerilog/test_errors.py b/myhdl/test/toVerilog/test_errors.py
index 44661aa0..2438854e 100644
--- a/myhdl/test/toVerilog/test_errors.py
+++ b/myhdl/test/toVerilog/test_errors.py
@@ -157,7 +157,7 @@ def h2(cnt):
     return 1
 
 def taskReturnVal(count, enable, clock, reset, n):
-    cnt = intbv()[8:]
+    cnt = intbv(0)[8:]
     while 1:
         yield posedge(clock), negedge(reset)
         if reset == ACTIVE_LOW:
@@ -169,7 +169,7 @@ def taskReturnVal(count, enable, clock, reset, n):
 
 
 def printnlToFile(count, enable, clock, reset, n):
-    cnt = intbv()[8:]
+    cnt = intbv(0)[8:]
     while 1:
         yield posedge(clock), negedge(reset)
         if reset == ACTIVE_LOW:
@@ -180,7 +180,7 @@ def printnlToFile(count, enable, clock, reset, n):
                 count.next = count + 1
 
 def printToFile(count, enable, clock, reset, n):
-    cnt = intbv()[8:]
+    cnt = intbv(0)[8:]
     while 1:
         yield posedge(clock), negedge(reset)
         if reset == ACTIVE_LOW:
@@ -191,25 +191,25 @@ def printToFile(count, enable, clock, reset, n):
                 count.next = count + 1
 
 def listComp1(count, enable, clock, reset, n):
-    mem = [intbv()[8:] for i in range(4) for j in range(5)]
+    mem = [intbv(0)[8:] for i in range(4) for j in range(5)]
     while 1:
         yield posedge(clock), negedge(reset)
         count.next = count + 1
 
 def listComp2(count, enable, clock, reset, n):
-    mem = [intbv()[8:] for i in downrange(4)]
+    mem = [intbv(0)[8:] for i in downrange(4)]
     while 1:
         yield posedge(clock), negedge(reset)
         count.next = count + 1
 
 def listComp3(count, enable, clock, reset, n):
-    mem = [intbv()[8:] for i in range(1, 4)]
+    mem = [intbv(0)[8:] for i in range(1, 4)]
     while 1:
         yield posedge(clock), negedge(reset)
         count.next = count + 1
         
 def listComp4(count, enable, clock, reset, n):
-    mem = [intbv() for i in range(4)]
+    mem = [intbv(0) for i in range(4)]
     while 1:
         yield posedge(clock), negedge(reset)
         count.next = count + 1
diff --git a/myhdl/test/toVerilog/test_infer.py b/myhdl/test/toVerilog/test_infer.py
index 7bbbce23..9f1b9349 100644
--- a/myhdl/test/toVerilog/test_infer.py
+++ b/myhdl/test/toVerilog/test_infer.py
@@ -166,24 +166,26 @@ class TestErrors(unittest.TestCase):
 
 
 def Infer1(a, out):
-    yield a
-    c = 5
-    c = a < 4
-    c = bool(0)
-    c = False
-    c = not a
-    c = True
-    out.next = c
+    while 1:
+        yield a
+        c = 5
+        c = a < 4
+        c = bool(0)
+        c = False
+        c = not a
+        c = True
+        out.next = c
     
 def Infer2(a, out):
-    yield a
-    c = a < 4
-    c = bool(0)
-    c = False
-    c = not a
-    c = True
-    c = 5
-    out.next = c
+    while 1:
+        yield a
+        c = a < 4
+        c = bool(0)
+        c = False
+        c = not a
+        c = True
+        c = 5
+        out.next = c
 
 def Infer3Func(a):
     if True:
@@ -192,37 +194,41 @@ def Infer3Func(a):
         return 5
 
 def Infer3(a, out):
-    yield a
-    out.next = Infer3Func(a)
+    while 1:
+        yield a
+        out.next = Infer3Func(a)
     
 def Infer4Func(a):
-    if True:
-        return 6
-    else:
-        return a < 3
+    while 1:
+        if True:
+            return 6
+        else:
+            return a < 3
 
 def Infer4(a, out):
-    yield a
-    out.next = Infer4Func(a)
+    while 1:
+        yield a
+        out.next = Infer4Func(a)
 
 def Infer5(a, out):
-    yield a
-    c = a + 1
-    c = a - 1
-    c = a * 3
-    c = a // 2
-    c = a << 2
-    c = a >> 2
-    c = a % 16
-    c = + a
-    c = -( - a)
-    c = ~(-3)
-    c = not a
-    c = 5 & 4
-    c = 5 | 2
-    c = 6 ^ 3
-    c = bool(a and 1)
-    out.next = c
+    while 1:
+        yield a
+        c = a + 1
+        c = a - 1
+        c = a * 3
+        c = a // 2
+        c = a << 2
+        c = a >> 2
+        c = a % 16
+        c = + a
+        c = -( - a)
+        c = ~(-3)
+        c = not a
+        c = 5 & 4
+        c = 5 | 2
+        c = 6 ^ 3
+        c = bool(a and 1)
+        out.next = c
 
 
         
@@ -233,7 +239,7 @@ class TestInfer(unittest.TestCase):
 
     def bench(self, Infertest):
         
-        a = Signal(intbv(-1)[16:])
+        a = Signal(intbv()[16:])
         out_v = Signal(intbv(0)[16:])
         out = Signal(intbv(0)[16:])
 
@@ -246,6 +252,7 @@ class TestInfer(unittest.TestCase):
             yield delay(10)
             # print "%s %s" % (out, out_v)
             self.assertEqual(out, out_v)
+            raise StopSimulation
 
         return stimulus(), infertest_inst, infertest_v_inst
 
diff --git a/myhdl/test/toVerilog/test_loops.py b/myhdl/test/toVerilog/test_loops.py
index eeec7663..0941b5a7 100644
--- a/myhdl/test/toVerilog/test_loops.py
+++ b/myhdl/test/toVerilog/test_loops.py
@@ -143,7 +143,7 @@ def ReturnFromTask(a, out):
     out[:] = 23 # to notice it
 
 def TaskCall(a, out):
-    var = intbv()[8:]
+    var = intbv(0)[8:]
     while 1:
         yield a
         ReturnFromTask(a, var)
diff --git a/myhdl/test/toVerilog/test_misc.py b/myhdl/test/toVerilog/test_misc.py
index 33263254..f08ce163 100644
--- a/myhdl/test/toVerilog/test_misc.py
+++ b/myhdl/test/toVerilog/test_misc.py
@@ -72,8 +72,8 @@ class TestConstWires(unittest.TestCase):
     def benchIntbv(self, ConstWire):
         
         p = Signal(intbv(0)[8:])
-        q = Signal(intbv()[8:])
-        q_v = Signal(intbv()[8:])
+        q = Signal(intbv(0)[8:])
+        q_v = Signal(intbv(0)[8:])
 
         constwire_inst = toVerilog(ConstWire, p, q)
         constwire_v_inst = ConstWire_v(ConstWire.func_name, p, q_v)
diff --git a/myhdl/test/toVerilog/test_signed.py b/myhdl/test/toVerilog/test_signed.py
new file mode 100644
index 00000000..d8f536a3
--- /dev/null
+++ b/myhdl/test/toVerilog/test_signed.py
@@ -0,0 +1,223 @@
+import os
+path = os.path
+import unittest
+from unittest import TestCase
+import random
+from random import randrange
+random.seed(2)
+
+from myhdl import *
+
+from util import setupCosimulation
+
+def binaryOps(
+##               Bitand,
+##               Bitor,
+##               Bitxor,
+##               FloorDiv,
+##               LeftShift,
+##               Mod,
+              Mul,
+##               Pow,
+##               RightShift,
+##               Sub,
+              Sum,
+##               EQ,
+##               NE,
+##               LT,
+##               GT,
+##               LE,
+##               GE,
+##               And,
+##               Or,
+              left, right):
+    while 1:
+        yield left, right
+##         Bitand.next = left & right
+##         Bitor.next = left | right
+##         Bitxor.next = left ^ right
+##         if right != 0:
+##             FloorDiv.next = left // right
+##         if left < 256 and right < 40:
+##             LeftShift.next = left << right
+##         if right != 0:
+##             Mod.next = left % right
+        Mul.next = left * right
+##         # Icarus doesn't support ** yet
+##         #if left < 256 and right < 40:
+##         #    Pow.next = left ** right
+##         Pow.next = 0
+##         RightShift.next = left >> right
+##         if left >= right:
+##             Sub.next = left - right
+        Sum.next = left + right
+##         EQ.next = left == right
+##         NE.next = left != right
+##         LT.next = left < right
+##         GT.next = left > right
+##         LE.next = left <= right
+##         GE.next = left >= right
+##         And.next = bool(left and right)
+##         Or.next = bool(left or right)
+
+
+
+def binaryOps_v(name,
+##                 Bitand,
+##                 Bitor,
+##                 Bitxor,
+##                 FloorDiv,
+##                 LeftShift,
+##                 Mod,
+                Mul,
+##                 Pow,
+##                 RightShift,
+##                 Sub,
+                Sum,
+##                 EQ,
+##                 NE,
+##                 LT,
+##                 GT,
+##                 LE,
+##                 GE,
+##                 And,
+##                 Or,
+                left, right):
+    return setupCosimulation(**locals())
+
+class TestBinaryOps(TestCase):
+
+    def binaryBench(self, Ll, Ml, Lr, Mr):
+
+        left = Signal(intbv(min=Ll, max=Ml))
+        right = Signal(intbv(min=Lr, max=Mr))
+##         Bitand = Signal(intbv(0)[max(m, n):])
+##         Bitand_v = Signal(intbv(0)[max(m, n):])
+##         Bitor = Signal(intbv(0)[max(m, n):])
+##         Bitor_v = Signal(intbv(0)[max(m, n):])
+##         Bitxor = Signal(intbv(0)[max(m, n):])
+##         Bitxor_v = Signal(intbv(0)[max(m, n):])
+##         FloorDiv = Signal(intbv(0)[m:])
+##         FloorDiv_v = Signal(intbv(0)[m:])
+##         LeftShift = Signal(intbv(0)[64:])
+##         LeftShift_v = Signal(intbv(0)[64:])
+##         Mod = Signal(intbv(0)[m:])
+##         Mod_v = Signal(intbv(0)[m:])
+        Mul = Signal(intbv(0, min=-2**17, max=2**17))
+        Mul_v = Signal(intbv(0, min=-2**17, max=2**17))
+##         Pow = Signal(intbv(0)[64:])
+##         Pow_v = Signal(intbv(0)[64:])
+##         RightShift = Signal(intbv(0)[m:])
+##         RightShift_v = Signal(intbv(0)[m:])
+##         Sub = Signal(intbv(0)[max(m, n):])
+##         Sub_v = Signal(intbv(0)[max(m, n):])
+        Sum = Signal(intbv(min=Ll+Lr, max=Ml+Mr-1))
+        Sum_v = Signal(intbv(min=Ll+Lr, max=Ml+Mr-1))
+        Sum = Signal(intbv(min=-2**14, max=2**14))
+        Sum_v = Signal(intbv(min=-2**14, max=2**14))
+##         EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
+##         EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)]
+##         And, Or = [Signal(bool()) for i in range(2)]
+##         And_v, Or_v, = [Signal(bool()) for i in range(2)]
+
+        binops = toVerilog(binaryOps,
+##                            Bitand,
+##                            Bitor,
+##                            Bitxor,
+##                            FloorDiv,
+##                            LeftShift,
+##                            Mod,
+                           Mul,
+##                            Pow,
+##                            RightShift,
+##                            Sub,
+                           Sum,
+##                            EQ,
+##                            NE,
+##                            LT,
+##                            GT,
+##                            LE,
+##                            GE,
+##                            And,
+##                            Or,
+                           left, right)
+        binops_v = binaryOps_v(binaryOps.func_name,
+##                                Bitand_v,
+##                                Bitor_v,
+##                                Bitxor_v,
+##                                FloorDiv_v,
+##                                LeftShift_v,
+##                                Mod_v,
+                               Mul_v,
+##                                Pow_v,
+##                                RightShift_v,
+##                                Sub_v,
+                               Sum_v,
+##                                EQ_v,
+##                                NE_v,
+##                                LT_v,
+##                                GT_v,
+##                                LE_v,
+##                                GE_v,
+##                                And_v,
+##                                Or_v,
+                               left, right)
+
+        def stimulus():
+            for i in range(100):
+                left.next = randrange(Ll, Ml)
+                right.next = randrange(Lr, Mr)
+                yield delay(10)
+            for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
+                left.next = j
+                right.next = k
+                yield delay(10)
+
+        def check():
+            while 1:
+                yield left, right
+                yield delay(1)
+            
+                #print "%s %s %s %s" % (left, right, Mul, Mul_v)
+                #print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
+                #print "%s %s %s %s" % (left, right, Sum, Sum_v)
+                #print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
+##                 self.assertEqual(Bitand, Bitand_v)
+##                 self.assertEqual(Bitor, Bitor_v)
+##                 self.assertEqual(Bitxor, Bitxor_v)
+##                 self.assertEqual(FloorDiv, FloorDiv_v)
+##                 self.assertEqual(LeftShift, LeftShift_v)
+##                 self.assertEqual(Mod, Mod_v)
+                self.assertEqual(Mul, Mul_v)
+                # self.assertEqual(Pow, Pow_v)
+##                 self.assertEqual(RightShift, RightShift_v)
+##                 self.assertEqual(Sub, Sub_v)
+                self.assertEqual(Sum, Sum_v)
+##                 self.assertEqual(EQ, EQ_v)
+##                 self.assertEqual(NE, NE_v)
+##                 self.assertEqual(LT, LT_v)
+##                 self.assertEqual(GT, GT_v)
+##                 self.assertEqual(LE, LE_v)
+##                 self.assertEqual(GE, GE_v)
+##                 self.assertEqual(And, And_v)
+##                 self.assertEqual(Or, Or_v)
+
+        return binops, binops_v, stimulus(), check()
+    
+
+    def testBinaryOps(self):
+        for Ll, Ml, Lr, Mr in ( (-128, 128, -128, 128),
+                                (-53, 25, -23, 123),
+                                (-23, 145, -66, 12),
+                                (23, 34, -34, -16),
+                                (-54, -20, 45, 73),
+                                (-25, -12, -123, -66),
+                              ):
+            sim = self.binaryBench(Ll, Ml, Lr, Mr)
+            Simulation(sim).run()
+                
+
+if __name__ == '__main__':
+    unittest.main()
+
+
diff --git a/myhdl/test/toVerilog/util.py b/myhdl/test/toVerilog/util.py
index 07942641..14a56b02 100644
--- a/myhdl/test/toVerilog/util.py
+++ b/myhdl/test/toVerilog/util.py
@@ -3,7 +3,8 @@ path = os.path
 
 from myhdl import *
 
-def setupCosimulation(**kwargs):
+# Icarus
+def setupCosimulationIcarus(**kwargs):
     name = kwargs['name']
     objfile = "%s.o" % name
     if path.exists(objfile):
@@ -12,4 +13,14 @@ def setupCosimulation(**kwargs):
     os.system(analyze_cmd)
     simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
     return Cosimulation(simulate_cmd, **kwargs)
-    
+
+# cver
+def setupCosimulationCver(**kwargs):
+    name = kwargs['name']
+    cmd = "cver -q +loadvpi=../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \
+          "%s.v tb_%s.v " % (name, name)
+    return Cosimulation(cmd, **kwargs)
+
+
+setupCosimulation = setupCosimulationIcarus
+setupCosimulation = setupCosimulationCver