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error handling

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This commit is contained in:
jand 2006-09-15 14:21:58 +00:00
parent 627e8f2e11
commit 80c742a99f
1 changed files with 2 additions and 2 deletions
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4
myhdl/_toVHDL/_convert.py
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@ -473,9 +473,9 @@ class _ConvertVisitor(_ToVerilogMixin):
elif ds < 0:
pre, suf = "resize(", ", %s)" % ts
else:
assertNotImplementedError
raise NotImplementedError
else:
assertNotImplementedError
assert NotImplementedError
self.write(pre)
self.write("%s(" % op)
self.write(prel)