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Function name is fixed (#318)
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@ -83,7 +83,7 @@ signal:
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single: VHDL; signal assignment
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single: VHDL; signal assignment
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single: Verilog; non-blocking assignment
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single: Verilog; non-blocking assignment
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The clock driver function :func:`clk_driver` drives the clock signal. If defines
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The clock driver function :func:`drive_clk` drives the clock signal. If defines
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a generator that continuously toggles a clock signal after a certain delay. A
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a generator that continuously toggles a clock signal after a certain delay. A
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new value of a signal is specified by assigning to its ``next`` attribute. This
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new value of a signal is specified by assigning to its ``next`` attribute. This
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is the MyHDL equivalent of the VHDL signal assignment and the Verilog
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is the MyHDL equivalent of the VHDL signal assignment and the Verilog
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