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Function name is fixed (#318)

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Ahmet Anbar 2019-08-10 23:32:39 +03:00 committed by Keerthan Jaic
parent c3a74de25f
commit 829f6f94ed
1 changed files with 1 additions and 1 deletions
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doc/source/manual/intro.rst
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@ -83,7 +83,7 @@ signal:
single: VHDL; signal assignment
single: Verilog; non-blocking assignment
The clock driver function :func:`clk_driver` drives the clock signal. If defines
The clock driver function :func:`drive_clk` drives the clock signal. If defines
a generator that continuously toggles a clock signal after a certain delay. A
new value of a signal is specified by assigning to its ``next`` attribute. This
is the MyHDL equivalent of the VHDL signal assignment and the Verilog