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Remove unused variable

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This commit is contained in:
Jan Decaluwe 2016-01-30 08:00:39 +01:00
parent 1971a56a5c
commit 82f43f056d
4 changed files with 11 additions and 19 deletions
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2
myhdl/conversion/_analyze.py
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@ -1222,7 +1222,7 @@ def isboundmethod(m):
return ismethod(m) and m.__self__ is not None
def _analyzeTopFunc(top_inst, func, *args, **kwargs):
def _analyzeTopFunc(func, *args, **kwargs):
tree = _makeAST(func)
v = _AnalyzeTopFuncVisitor(func, tree, *args, **kwargs)
v.visit(tree)

18
myhdl/conversion/_toVHDL.py
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@ -170,8 +170,7 @@ class _ToVHDLConvertor(object):
_annotateTypes(genlist)
### infer interface
top_inst = h.hierarchy[0]
intf = _analyzeTopFunc(top_inst, func, *args, **kwargs)
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
# sanity checks on interface
for portname in intf.argnames:
@ -476,13 +475,13 @@ def _convertGens(genlist, siglist, memlist, vfile):
if w <= 31:
pre, suf = "to_signed(", ", %s)" % w
else:
pre, suf = "signed'(", ")"
pre, suf = "signed'(", ")"
c = '"%s"' % bin(c, w)
else:
if w <= 31:
pre, suf = "to_unsigned(", ", %s)" % w
else:
pre, suf = "unsigned'(", ")"
pre, suf = "unsigned'(", ")"
c = '"%s"' % bin(c, w)
else:
raise ToVHDLError("Unexpected type for constant signal", s._name)
@ -1093,7 +1092,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.write(';')
def visit_IfExp(self, node):
# propagate the node's vhd attribute
# propagate the node's vhd attribute
node.body.vhd = node.orelse.vhd = node.vhd
self.write('tern_op(')
self.write('cond => ')
@ -1310,7 +1309,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
if isinstance(node.vhd, vhd_int):
s = self.IntRepr(obj)
elif isinstance(node.vhd, vhd_boolean):
s = "%s" % bool(obj)
s = "%s" % bool(obj)
elif isinstance(node.vhd, vhd_std_logic):
s = "'%s'" % int(obj)
elif isinstance(node.vhd, vhd_unsigned):
@ -2257,10 +2256,3 @@ def _annotateTypes(genlist):
continue
v = _AnnotateTypesVisitor(tree)
v.visit(tree)

7
myhdl/conversion/_toVerilog.py
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@ -151,8 +151,8 @@ class _ToVerilogConvertor(object):
genlist = _analyzeGens(arglist, h.absnames)
siglist, memlist = _analyzeSigs(h.hierarchy)
_annotateTypes(genlist)
top_inst = h.hierarchy[0]
intf = _analyzeTopFunc(top_inst, func, *args, **kwargs)
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
doc = _makeDoc(inspect.getdoc(func))
@ -1570,6 +1570,3 @@ def _annotateTypes(genlist):
continue
v = _AnnotateTypesVisitor(tree)
v.visit(tree)

3
myhdl/test/conversion/toVHDL/Makefile
View File

@ -8,3 +8,6 @@ ghdl:
clean:
- rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* *.log *_ghdl
gitclean:
git clean -dfx