diff --git a/doc/source/manual/conversion.rst b/doc/source/manual/conversion.rst
index 19337c96..1a7fa575 100644
--- a/doc/source/manual/conversion.rst
+++ b/doc/source/manual/conversion.rst
@@ -538,6 +538,8 @@ The convertor supports this by ignoring all code that is embedded in a
 account.
 
 
+.. index:: single: user-defined code; description
+
 .. _conv-custom:
 
 User-defined code
diff --git a/doc/source/manual/conversion_examples.rst b/doc/source/manual/conversion_examples.rst
index e554b5c1..0f5cbaec 100644
--- a/doc/source/manual/conversion_examples.rst
+++ b/doc/source/manual/conversion_examples.rst
@@ -833,6 +833,8 @@ The VHDL output code is as follows::
     end architecture MyHDL;
 
 
+.. index:: single: user-defined code; example
+
 .. _conv-usage-custom:
 
 User-defined code