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Jan Decaluwe 2011-05-04 21:33:14 +02:00
commit 838dc47a13
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2
doc/source/manual/conversion.rst
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@ -538,6 +538,8 @@ The convertor supports this by ignoring all code that is embedded in a
account. account.
.. index:: single: user-defined code; description
.. _conv-custom: .. _conv-custom:
User-defined code User-defined code

2
doc/source/manual/conversion_examples.rst
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@ -833,6 +833,8 @@ The VHDL output code is as follows::
end architecture MyHDL; end architecture MyHDL;
.. index:: single: user-defined code; example
.. _conv-usage-custom: .. _conv-usage-custom:
User-defined code User-defined code