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Corrected error in which toVHDL wasn't being updated in the tests to actually set no_initial_value=False.

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Henry Gomersall 2016-02-26 20:55:15 +00:00
parent 0c315d3ae7
commit 843eb9eb4a
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GPG Key ID: 67F4313D73CED5A6
1 changed files with 6 additions and 4 deletions
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myhdl/test/conversion/general/test_initial_values.py
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@ -60,15 +60,17 @@ def initial_value_bench(initial_val, change_input_signal):
return clkgen, output_driver, compare_output
def runner(initial_val, change_input_signal=False):
pre_no_initial_value = toVerilog.no_initial_value
pre_toVerilog_no_initial_value = toVerilog.no_initial_value
pre_toVHDL_no_initial_value = toVerilog.no_initial_value
toVerilog.no_initial_value = False
toVHDL.no_initial_value = False
assert conversion.verify(
initial_value_bench, initial_val, change_input_signal) == 0
toVerilog.no_initial_value = pre_no_initial_value
toVerilog.no_initial_value = pre_toVerilog_no_initial_value
toVHDL.no_initial_value = pre_toVHDL_no_initial_value
def test_unsigned():
'''The correct initial value should be used for unsigned type signal.