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enabled initial value support

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This commit is contained in:
Christopher Felton 2015-06-12 10:53:43 -05:00
parent 254e458917
commit 87784ad240
2 changed files with 15 additions and 5 deletions
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8
myhdl/conversion/_toVHDL.py
View File

@ -100,6 +100,7 @@ class _ToVHDLConvertor(object):
"use_clauses",
"architecture",
"std_logic_ports",
"disable_initial_value"
)
def __init__(self):
@ -113,6 +114,7 @@ class _ToVHDLConvertor(object):
self.use_clauses = None
self.architecture = "MyHDL"
self.std_logic_ports = False
self.disable_initial_value = True
def __call__(self, func, *args, **kwargs):
global _converting
@ -403,8 +405,10 @@ def _writeSigDecls(f, intf, siglist, memlist):
category=ToVHDLWarning
)
# the following line implements initial value assignments
# print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val))
print("signal %s: %s%s;" % (s._name, p, r), file=f)
if toVHDL.disable_initial_value:
print("signal %s: %s%s;" % (s._name, p, r), file=f)
else:
print("signal %s: %s%s = %s;" % (s._name, p, r, int(s._val)), file=f)
elif s._read:
# the original exception
# raise ToVHDLError(_error.UndrivenSignal, s._name)

12
myhdl/conversion/_toVerilog.py
View File

@ -95,7 +95,8 @@ class _ToVerilogConvertor(object):
"no_myhdl_header",
"no_testbench",
"portmap",
"trace"
"trace",
"disable_initial_value"
)
def __init__(self):
@ -109,6 +110,7 @@ class _ToVerilogConvertor(object):
self.no_myhdl_header = False
self.no_testbench = False
self.trace = False
self.disable_initial_value = True
def __call__(self, func, *args, **kwargs):
global _converting
@ -289,8 +291,12 @@ def _writeSigDecls(f, intf, siglist, memlist):
if s._driven == 'reg':
k = 'reg'
# the following line implements initial value assignments
# print >> f, "%s %s%s = %s;" % (k, r, s._name, int(s._val))
print("%s %s%s%s;" % (k, p, r, s._name), file=f)
# don't initial value "wire", inital assignment to a wire
# equates to a continuous assignment [reference]
if toVerilog.disable_initial_value or k == 'wire':
print("%s %s%s%s;" % (k, p, r, s._name), file=f)
else:
print("%s %s%s%s = %s;" % (k, p, r, s._name, int(s._val)), file=f)
elif s._read:
# the original exception
# raise ToVerilogError(_error.UndrivenSignal, s._name)