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handle possible name conflict after renaming attr refs.

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--HG--
branch : 0.9-dev
This commit is contained in:
Keerthan Jaic 2013-09-16 15:21:37 -04:00
parent 30a932d5b9
commit 885a741889
1 changed files with 4 additions and 0 deletions
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4
myhdl/conversion/_analyze.py
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@ -110,6 +110,8 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
if isinstance(s, _SliceSignal):
continue
s._name = _makeName(n, prefixes)
while s._name in sigdict:
s._name += '_'
if not s._nrbits:
raise ConversionError(_error.UndefinedBitWidth, s._name)
# slice signals
@ -121,6 +123,8 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
if m.name is not None:
continue
m.name = _makeName(n, prefixes)
while m.name in memdict:
m.name += '_'
memlist.append(m)
# handle the case where a named signal appears in a list also by giving