fsm test

myhdl/_enum.py

@@ -111,6 +111,8 @@ def enum(*args, **kwargs):
             return self._declared
         def _setDeclared(self):
             self.__dict__['_declared'] = True
+        def _clearDeclared(self):
+            self.__dict__['_declared'] = False
         _toVHDL = __str__
         def _toVHDL(self, name):
             typename = "t_enum_%s" % name

myhdl/_toVHDL/_convert.py

@@ -53,6 +53,7 @@ from myhdl._Signal import _WaiterList
             
 _converting = 0
 _profileFunc = None
+_enumTypeList = []
 
 def _checkArgs(arglist):
     for arg in arglist:
@@ -126,6 +127,11 @@ class _ToVHDLConvertor(object):
         # clean up signal names
         for sig in siglist:
             sig._name = None
+            sig._driven = False
+            sig._read = False
+        # clean up enum type names
+        for enumType in _enumTypeList:
+            enumType._clearDeclared()
 
         return h.top
     
@@ -223,6 +229,7 @@ def _declareEnumType(f, s):
     else:
         print >> f, enumType._toVHDL(s._name)
         enumType._setDeclared()
+        _enumTypeList.append(enumType)
 
     
 def _getRangeString(s):
@@ -299,7 +306,9 @@ class _ConvertVisitor(_ToVerilogMixin):
     def writeDeclaration(self, obj, name, dir):
         if dir: dir = dir + ' '
         if type(obj) is bool:
-            self.write("%s%s" % (dir, name))
+            self.write("%s%s: std_logic" % (dir, name))
+        elif isinstance(obj, EnumItemType):
+            self.write("%s%s: %s" % (dir, name, obj._type._name))
         elif isinstance(obj, int):
             if dir == "input ":
                 self.write("input %s;" % name)
@@ -775,6 +784,9 @@ class _ConvertVisitor(_ToVerilogMixin):
         elif n in self.ast.vardict:
             addSignBit = isMixedExpr
             s = n
+            obj = self.ast.vardict[n]
+            if isinstance(obj, intbv) and isinstance(node.vhdlObj, vhdl_integer):
+                s = "to_integer(%s)" % n
         elif n in self.ast.argnames:
             assert n in self.ast.symdict
             addSignBit = isMixedExpr
@@ -953,7 +965,7 @@ class _ConvertVisitor(_ToVerilogMixin):
         self.visit(node.value, _context.YIELD)
         self.write(";")
 
-    def manageEdges(self, node, senslist):
+    def manageEdges(self, ifnode, senslist):
         """ Helper method to convert MyHDL style template into VHDL style"""
         first = senslist[0]
         if isinstance(first, _WaiterList):
@@ -967,7 +979,7 @@ class _ConvertVisitor(_ToVerilogMixin):
             if not isinstance(e, bt):
                 self.raiseError(node, "base type error in sensitivity list")
         if len(senslist) >= 2 and bt == _WaiterList:
-            ifnode = node.code.nodes[0]
+            # ifnode = node.code.nodes[0]
             assert isinstance(ifnode, astNode.If)
             asyncEdges = []
             for test, suite in ifnode.tests:
@@ -1110,7 +1122,7 @@ class _ConvertAlwaysDecoVisitor(_ConvertVisitor):
     def visitFunction(self, node, *args):
         assert self.ast.senslist
         senslist = self.ast.senslist
-        senslist = self.manageEdges(node, senslist)
+        senslist = self.manageEdges(node.code.nodes[0], senslist)
 ##         first = senslist[0]
 ##         if isinstance(first, _WaiterList):
 ##             bt = _WaiterList

myhdl/test/core/Makefile

@@ -0,0 +1,2 @@
+all:
+	python test_all.py

myhdl/test/toVHDL/test_fsm.py

@@ -199,6 +199,7 @@ def FSMBench(FramerCtrl, t_State):
 
 
 verifyConversion(FSMBench, FramerCtrl, t_State_b)
+verifyConversion(FSMBench, FramerCtrl_alt, t_State_b)
 
 ## def testRef(self):
 ##     for t_State in (t_State_b, t_State_oc, t_State_oh):

myhdl/test/toVHDL/test_inc.py

@@ -106,7 +106,7 @@ def incTaskFreeVar(count, enable, clock, reset, n):
     return incTaskGen
 
 
-def tb_inc():
+def tb_inc(inc):
 
     NR_CYCLES = 201
       
@@ -143,7 +143,9 @@ def tb_inc():
 
 
     
-verifyConversion(tb_inc) 
+verifyConversion(tb_inc, incRef) 
+verifyConversion(tb_inc, inc) 
+verifyConversion(tb_inc, inc2)