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This commit is contained in:
jand 2007-06-25 18:36:30 +00:00
parent 64e602e043
commit 8ac1ab0cff
4 changed files with 10 additions and 1 deletions
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3
myhdl/test/toVHDL/GHDL.py Normal file
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from myhdl.conversion import verify
verify.simulator = "GHDL"

3
myhdl/test/toVHDL/cver.py Normal file
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from myhdl.conversion import verify
verify.simulator = "cver"

3
myhdl/test/toVHDL/icarus.py Normal file
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from myhdl.conversion import verify
verify.simulator = "icarus"

2
myhdl/test/toVHDL/test_bin2gray.py
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@ -56,7 +56,7 @@ def bin2grayBench(width, bin2gray):
#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
#print bin(G, width)
#print bin(G_v, width)
print G
print "%0d" % G
return stimulus, bin2gray_inst