From 8ac1ab0cff296981933e189afd294180c96a4842 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Mon, 25 Jun 2007 18:36:30 +0000
Subject: [PATCH] sim files

---
 myhdl/test/toVHDL/GHDL.py          | 3 +++
 myhdl/test/toVHDL/cver.py          | 3 +++
 myhdl/test/toVHDL/icarus.py        | 3 +++
 myhdl/test/toVHDL/test_bin2gray.py | 2 +-
 4 files changed, 10 insertions(+), 1 deletion(-)
 create mode 100644 myhdl/test/toVHDL/GHDL.py
 create mode 100644 myhdl/test/toVHDL/cver.py
 create mode 100644 myhdl/test/toVHDL/icarus.py

diff --git a/myhdl/test/toVHDL/GHDL.py b/myhdl/test/toVHDL/GHDL.py
new file mode 100644
index 00000000..7532ebc7
--- /dev/null
+++ b/myhdl/test/toVHDL/GHDL.py
@@ -0,0 +1,3 @@
+from myhdl.conversion import verify
+
+verify.simulator = "GHDL"
diff --git a/myhdl/test/toVHDL/cver.py b/myhdl/test/toVHDL/cver.py
new file mode 100644
index 00000000..3b269c83
--- /dev/null
+++ b/myhdl/test/toVHDL/cver.py
@@ -0,0 +1,3 @@
+from myhdl.conversion import verify
+
+verify.simulator = "cver"
diff --git a/myhdl/test/toVHDL/icarus.py b/myhdl/test/toVHDL/icarus.py
new file mode 100644
index 00000000..a56aeb4a
--- /dev/null
+++ b/myhdl/test/toVHDL/icarus.py
@@ -0,0 +1,3 @@
+from myhdl.conversion import verify
+
+verify.simulator = "icarus"
diff --git a/myhdl/test/toVHDL/test_bin2gray.py b/myhdl/test/toVHDL/test_bin2gray.py
index 27bcf1d9..4cf66644 100644
--- a/myhdl/test/toVHDL/test_bin2gray.py
+++ b/myhdl/test/toVHDL/test_bin2gray.py
@@ -56,7 +56,7 @@ def bin2grayBench(width, bin2gray):
             #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
             #print bin(G, width)
             #print bin(G_v, width)
-            print G
+            print "%0d" % G
 
 
     return stimulus, bin2gray_inst