diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py
index b742fa70..1f4f1760 100644
--- a/myhdl/_Simulation.py
+++ b/myhdl/_Simulation.py
@@ -33,7 +33,7 @@ from myhdl import delay, Signal, Cosimulation, join
 from myhdl import _simulator
 from myhdl._simulator import _siglist, _futureEvents
 from myhdl._Waiter import _Waiter, _WaiterList
-from myhdl._util import StopSimulation, SuspendSimulation
+from myhdl._util import StopSimulation, SuspendSimulation, _flatten, _printExcInfo
 from myhdl._Error import Error
 
 
@@ -62,7 +62,8 @@ class Simulation(object):
 
         """
         _simulator._time = 0
-        self._waiters, self._cosim = _flatten(*args)
+        arglist = _flatten(*args)
+        self._waiters, self._cosim = _checkArgs(arglist)
         if not self._cosim and _simulator._cosim:
             warn("Cosimulation not registered as Simulation argument")
         del _futureEvents[:]
@@ -184,52 +185,33 @@ class Simulation(object):
 
             except SuspendSimulation:
                 if not quiet:
-                    printExcInfo()
+                    _printExcInfo()
                 if tracing:
                     tracefile.flush()
                 return 1
 
             except StopSimulation:
                 if not quiet:
-                    printExcInfo()
+                    _printExcInfo()
                 self._finalize()
                 return 0
 
             except:
                 self._finalize()
                 raise
-        
+                
 
-
-def printExcInfo():
-    kind, value, traceback = sys.exc_info()
-    msg = str(kind)
-    msg = msg[msg.rindex('.')+1:]
-    if str(value):
-        msg += ": %s" % value
-        print msg
-        
-     
-def _flatten(*args):
+def _checkArgs(arglist):
     waiters = []
     cosim = None
-    for arg in args:
+    for arg in arglist:
         if type(arg) is GeneratorType:
             waiters.append(_Waiter(arg))
         elif type(arg) is Cosimulation:
-            if cosim:
+            if cosim is not None:
                 raise MultipleCosimError
             cosim = arg
-            waiters.append(_Waiter(cosim._waiter()))
-        elif isinstance(arg, (list, tuple)):
-            for item in arg:
-                w, c = _flatten(item)
-                if cosim and c:
-                    raise MultipleCosimError
-                if c:
-                    cosim = c
-                waiters.extend(w)
         else:
             raise ArgTypeError(str(type(arg)))
     return waiters, cosim
-
+        
diff --git a/myhdl/_enum.py b/myhdl/_enum.py
index c8c710d7..e41102da 100644
--- a/myhdl/_enum.py
+++ b/myhdl/_enum.py
@@ -27,7 +27,7 @@ __date__ = "$Date$"
 
 from types import StringType
 
-from myhdl._util import bin
+from myhdl._bin import bin
 
 def enum(*args):
 
diff --git a/myhdl/_toVerilog.py b/myhdl/_toVerilog.py
index 7adad75b..526febc0 100644
--- a/myhdl/_toVerilog.py
+++ b/myhdl/_toVerilog.py
@@ -386,8 +386,9 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
             n = target.name
             obj = self.getObj(expr)
             if obj is None:
-                self.raiseError(node, "Cannot infer type of %s" % n)
+                self.raiseError(node, "Cannot infer type or bit width of %s" % n)
             self.vardict[n] = obj
+            # XXX if n is already in vardict
 
     def visitAssName(self, node, *args):
         n = node.name
diff --git a/myhdl/_util.py b/myhdl/_util.py
index d597a850..d7b30b2b 100644
--- a/myhdl/_util.py
+++ b/myhdl/_util.py
@@ -35,6 +35,7 @@ import exceptions
 import sys
 import inspect
 import re
+from sets import Set
 from types import FunctionType, GeneratorType, ListType, TupleType
 import compiler
 # hope this will always work ...
@@ -42,32 +43,9 @@ from compiler.consts import CO_GENERATOR
 
 from myhdl._Cosimulation import Cosimulation
 
-
 def downrange(start, stop=0):
     """ Return a downward range. """
     return range(start-1, stop-1, -1)
-
-def _int2bitstring(num):
-    if num == 0:
-        return '0'
-    if abs(num) == 1:
-        return '1'
-    return _int2bitstring(num // 2) + _int2bitstring(num % 2)
-
-def bin(num, width=0):
-    """Return a binary string representation.
-
-    num -- number to convert
-    Optional parameter:
-    width -- specifies the desired string (sign bit padding)
-    """
-    num = long(num)
-    s = _int2bitstring(num)
-    pad = '0'
-    if num < 0:
-        pad = '1'
-    return (width - len(s)) * pad + s
-
         
 class StopSimulation(exceptions.Exception):
     """ Basic exception to stop a Simulation """
@@ -77,7 +55,7 @@ class SuspendSimulation(exceptions.Exception):
     """ Basic exception to suspend a Simulation """
     pass
 
-def printExcInfo():
+def _printExcInfo():
     kind, value  = sys.exc_info()[:2]
     msg = str(kind)
     msg = msg[msg.rindex('.')+1:]
@@ -85,7 +63,6 @@ def printExcInfo():
         msg += ": %s" % value
         print msg
        
-
 def _isGenSeq(obj):
     if type(obj) in (GeneratorType, Cosimulation):
         return 1
@@ -96,9 +73,18 @@ def _isGenSeq(obj):
             return 0
     return 1
 
-        
 def _isGenFunc(obj):
     if type(obj) is FunctionType:
         return bool(obj.func_code.co_flags & CO_GENERATOR)
     return bool(0)
 
+def _flatten(*args):
+    arglist = []
+    for arg in args:
+        if isinstance(arg, (list, tuple, Set)):
+            for item in arg:
+                arglist.extend(_flatten(item))
+        else:
+            arglist.append(arg)
+    return arglist
+
diff --git a/myhdl/test/test_Simulation.py b/myhdl/test/test_Simulation.py
index 4882b56d..195fc583 100644
--- a/myhdl/test/test_Simulation.py
+++ b/myhdl/test/test_Simulation.py
@@ -23,7 +23,6 @@ __author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
 __revision__ = "$Revision$"
 __date__ = "$Date$"
 
-from __future__ import generators
 import unittest
 from unittest import TestCase
 import random