added second interfaces test

--HG--
branch : mep107

myhdl/__init__.py

@@ -50,7 +50,7 @@ toVerilog -- function that converts a design to Verilog
 
 """
 
-__version__ = "0.8"
+__version__ = "0.9dev"
 
 import sys
 import warnings

myhdl/conversion/_verify.py

@@ -49,8 +49,8 @@ registerSimulator(
     name="GHDL",
     hdl="VHDL",
     analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
-    elaborate="ghdl -e --workdir=work -o %(unitname)s_ghdl %(topname)s",
-    simulate="ghdl -r %(unitname)s_ghdl"
+    elaborate="ghdl -e --workdir=work -o %(unitname)s %(topname)s",
+    simulate="ghdl -r --workdir=work %(unitname)s"
     )
 
 
@@ -140,6 +140,7 @@ class  _VerificationClass(object):
                 except:
                     pass
 
+        print(analyze)
         ret = subprocess.call(analyze, shell=True)
         if ret != 0:
             print >> sys.stderr, "Analysis failed"
@@ -165,12 +166,14 @@ class  _VerificationClass(object):
 
 
         if elaborate is not None:
+            print(elaborate)
             ret = subprocess.call(elaborate, shell=True)
             if ret != 0:
                 print >> sys.stderr, "Elaboration failed"
                 return ret
             
         g = tempfile.TemporaryFile()
+        print(simulate)
         ret = subprocess.call(simulate, stdout=g, shell=True)
     #    if ret != 0:
     #        print "Simulation run failed"

myhdl/test/conversion/general/test_interfaces1.py

@@ -1,5 +1,5 @@
 
-from pprint import pprint
+import sys
 
 from myhdl import *
 from myhdl import ConversionError
@@ -86,8 +86,6 @@ def c_testbench_two():
         yield delay(17)
         for ii in range(7):
             yield clock.posedge
-        #pprint(vars(ia))
-        #pprint(vars(ib))
         assert ia.x == 5
         assert ia.y == 7
         print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y))
@@ -117,5 +115,9 @@ def test_two_level_verify():
 
 
 if __name__ == '__main__':
+    print(sys.argv[1])
+    verify.simulator = analyze.simulator = sys.argv[1]
     Simulation(c_testbench_one()).run()
     Simulation(c_testbench_two()).run()
+    print(verify(c_testbench_one))
+    print(verify(c_testbench_two))

myhdl/test/conversion/general/test_interfaces2.py

@@ -0,0 +1,104 @@
+
+import sys
+
+from myhdl import *
+from myhdl.conversion import analyze,verify
+
+class Intf(object):
+    def __init__(self):
+        self.x = Signal(intbv(1,min=-111,max=111))
+        self.y = Signal(intbv(2,min=-211,max=211))
+        self.z = Signal(intbv(3,min=-311,max=311))
+
+def m_modify(clock,reset,a):
+
+    intfa = Intf()
+
+    @always_seq(clock.posedge,reset=reset)
+    def rtl_inc():
+        intfa.x.next = intfa.x + 1
+        intfa.y.next = intfa.y + 2
+        intfa.z.next = intfa.z + 3
+
+    @always_comb
+    def rtl_add():
+        a.x.next = intfa.x + 1
+        a.y.next = intfa.y + 2
+        a.z.next = intfa.z + 3
+
+    return rtl_inc,rtl_add
+
+def m_test_intf(clock,reset,a,b,c):
+
+    intfa = Intf()
+    intfaa = Intf()
+
+    gen_mod = m_modify(clock,reset,intfaa)
+    
+    @always_seq(clock.posedge,reset=reset)
+    def rtl_inc():
+        intfa.x.next = intfa.x - 1
+        intfa.y.next = intfa.y - 2
+        intfa.z.next = intfa.z - 3
+
+        b.x.next = b.x + 1
+        b.y.next = b.y + 2
+        b.z.next = b.z + 3
+
+        c.x.next = c.x + 1
+        c.y.next = c.y + 2
+        c.z.next = c.z + 3
+
+    @always_comb
+    def rtl_combine():
+        a.x.next = intfaa.x + 1
+        a.y.next = intfaa.y + 2
+        a.z.next = intfaa.z + 3
+
+    return gen_mod,rtl_inc,rtl_combine
+
+
+def c_testbench():
+    clock = Signal(bool(0))
+    reset = ResetSignal(0, active=0, async=False)
+    a,b,c = (Intf(),Intf(),Intf(),)
+
+    tb_dut = m_test_intf(clock,reset,a,b,c)
+
+    @instance
+    def tb_clk():
+        clock.next = False
+        yield delay(10)
+        while True:
+            clock.next = not clock
+            yield delay(10)
+
+    @instance
+    def tb_stim():
+        reset.next = False
+        yield delay(23)
+        reset.next = True
+        yield delay(33)
+        for ii in range(7):
+            print("a: x=%d y=%d z=%d"%(a.x,a.y,a.z))
+            print("b: x=%d y=%d z=%d"%(b.x,b.y,b.z))
+            print("c: x=%d y=%d z=%d"%(c.x,c.y,c.z))
+            yield clock.posedge
+        raise StopSimulation
+
+    return tb_dut,tb_clk,tb_stim
+
+def test_name_conflicts_analyze():
+    clock = Signal(bool(0))
+    reset = ResetSignal(0, active=0, async=False)
+    a,b,c = (Intf(),Intf(),Intf(),)
+    analyze(m_test_intf,clock,reset,a,b,c)
+
+def test_name_conflicts_verify():
+    assert verify(c_testbench) == 0
+
+if __name__ == '__main__':
+    verify.simulator = analyze.simulator = sys.argv[1]
+    Simulation(c_testbench()).run()
+    print(verify(c_testbench))
+