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Made the initial value assignment for the LoS case much less verbose for the common case where all the values are the same.

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This commit is contained in:
Henry Gomersall 2016-05-06 17:54:25 +01:00
parent 1b61a25759
commit 8d386aac23
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GPG Key ID: 67F4313D73CED5A6
3 changed files with 57 additions and 10 deletions
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13
myhdl/conversion/_toVHDL.py
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@ -467,11 +467,16 @@ def _writeSigDecls(f, intf, siglist, memlist):
else:
sig_vhdl_objs = [inferVhdlObj(each) for each in m.mem]
_val_str = ',\n '.join(
['%dX"%s"' % (obj.size, str(each._init)) for
obj, each in zip(sig_vhdl_objs, m.mem)])
if all([each._init == m.mem[0]._init for each in m.mem]):
val_str = (
' := (others => %dX"%s")' %
(sig_vhdl_objs[0].size, str(m.mem[0]._init)))
else:
_val_str = ',\n '.join(
['%dX"%s"' % (obj.size, str(each._init)) for
obj, each in zip(sig_vhdl_objs, m.mem)])
val_str = ' := (\n ' + _val_str + ')'
val_str = ' := (\n ' + _val_str + ')'
print("type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r), file=f)
print("signal %s: %s%s;" % (m.name, t, val_str), file=f)

30
myhdl/conversion/_toVerilog.py
View File

@ -27,6 +27,7 @@ from __future__ import print_function
import sys
import math
import os
import textwrap
import inspect
from datetime import datetime
@ -369,11 +370,30 @@ def _writeSigDecls(f, intf, siglist, memlist):
k = m._driven
if toVerilog.initial_values:
val_assignments = '\n'.join(
[' %s[%d] <= %s;' % (m.name, n, _intRepr(each._init))
for n, each in enumerate(m.mem)])
initial_assignments = (
'initial begin\n' + val_assignments + '\nend')
if all([each._init == m.mem[0]._init for each in m.mem]):
initialize_block_name = ('INITIALIZE_' + m.name).upper()
_initial_assignments = (
'''
initial begin: %s
integer i;
for(i=0; i<%d; i=i+1) begin
%s[i] = %s;
end
end
''' % (initialize_block_name, len(m.mem), m.name,
_intRepr(m.mem[0]._init)))
initial_assignments = (
textwrap.dedent(_initial_assignments))
else:
val_assignments = '\n'.join(
[' %s[%d] <= %s;' %
(m.name, n, _intRepr(each._init))
for n, each in enumerate(m.mem)])
initial_assignments = (
'initial begin\n' + val_assignments + '\nend')
print("%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth),
file=f)

24
myhdl/test/conversion/general/test_initial_values.py
View File

@ -288,19 +288,29 @@ def test_unsigned_list():
runner(initial_vals, tb=initial_value_list_bench)
# All the same case
initial_vals = [
intbv(randrange(min_val, max_val), min=min_val, max=max_val)] * 10
runner(initial_vals, tb=initial_value_list_bench)
def test_signed_list():
'''The correct initial value should be used for signed type signal lists
'''
min_val = -12
max_val = 4
initial_vals = [intbv(
randrange(min_val, max_val), min=min_val, max=max_val)
for each in range(10)]
runner(initial_vals, tb=initial_value_list_bench)
# All the same case
initial_vals = [intbv(
randrange(min_val, max_val), min=min_val, max=max_val)] * 10
runner(initial_vals, tb=initial_value_list_bench)
def test_modbv_list():
'''The correct initial value should be used for modbv type signal lists
'''
@ -310,6 +320,11 @@ def test_modbv_list():
runner(initial_vals, tb=initial_value_list_bench)
# All the same case
initial_vals = [modbv(randrange(0, 2**10))[10:]] * 10
runner(initial_vals, tb=initial_value_list_bench)
def test_long_signals_list():
'''The correct initial value should work with wide bitwidths (i.e. >32)
signal lists
@ -322,6 +337,10 @@ def test_long_signals_list():
runner(initial_vals, tb=initial_value_list_bench)
# All the same case
initial_vals = [intbv(2**65-50, min=min_val, max=max_val)] * 10
runner(initial_vals, tb=initial_value_list_bench)
def test_bool_signals_list():
'''The correct initial value should be used for a boolean type signal lists
'''
@ -329,6 +348,9 @@ def test_bool_signals_list():
runner(initial_vals, tb=initial_value_list_bench)
initial_vals = [intbv(0, min=0, max=2)] * 10
runner(initial_vals, tb=initial_value_list_bench)
def test_init_used():
'''It should be the _init attribute that is used for initialisation