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registration doc update
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Jan Decaluwe
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@ -123,7 +123,7 @@ MyHDL types are mapped to VHDL types according to the following table:
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+--------------------------------------------------+-----------------------------------+
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| ``enum`` | dedicated enumeration type |
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+--------------------------------------------------+-----------------------------------+
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| ``tuple``of ``int`` | mapped to case statement |
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| ``tuple`` of ``int`` | mapped to case statement |
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+--------------------------------------------------+-----------------------------------+
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| ``list`` of ``bool`` | ``array`` of ``std_logic`` |
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+--------------------------------------------------+-----------------------------------+
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@ -257,7 +257,7 @@ caused regular user complaints. In this release, this restriction has
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been lifted.
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.. _new-test:
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.. _new06-test:
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Conversion of test benches
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@ -416,7 +416,7 @@ To verify the convertor output, a methodology has been developed and
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implemented that doesn't rely on co-simulation and works for both
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Verilog and VHDL.
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The solution builds on the features explained in section :ref:`new-test`.
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The solution builds on the features explained in section :ref:`new06-test`.
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The idea is basically to convert the test bench as well as the
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functional code. In particular, ``print`` statements in MyHDL are
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converted to equivalent statements in the HDL. The verification
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@ -464,7 +464,7 @@ The two previous functions have the following attribute:
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.. attribute:: verify.simulator
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Used to set the name of the HDL simulator. GHDL simulator
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Used to set the name of the HDL simulator. GHDL
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is the default.
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HDL simulator registration
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@ -475,17 +475,22 @@ be registered first. This is needed once per simulator (or rather, per
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set of analysis and simulation commands). Registering is done with the
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following function:
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.. function:: registerSimulator(name=None, analyze=None, elaborate=None, simulate=None)
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.. function:: registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulate=None, offset=0)
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Registers a particular HDL simulator to be used by :func:`verify()`
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and :func:`analyze()`. *name* is the name of the simulator.
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*hdl* specifies the HDL: ``"VHDL"`` or ``"Verilog"``.
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*analyze* is a command string to analyze the HDL source code.
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*elaborate* is a command string to elaborate the HDL
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code. This command is optional.
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*simulate* is a command string to simulate the HDL code.
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*offset* is an integer specifying the number of initial lines to be ignored
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from the HDL simulator output.
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The command strings should be string templates that refer to the
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``topname`` variable that specifies the design name.
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``topname`` variable that specifies the design name. The templates
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can also use the ``unitname`` variable which is the lower case
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version of ``topname``.
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The command strings can assume that a subdirectory called
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``work`` is available in the current working directory. Analysis and
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elaboration results can be put there if desired.
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@ -498,20 +503,45 @@ following function:
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registration can be overwritten if required.
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Example
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^^^^^^^
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Example: preregistered HDL simulators
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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As an example of registering a HDL simulator, we will show how the
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GHDL simulator is registered in the MyHDL distribution. The command is
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the following::
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A number of open-source HDL simulators are preregistered in the
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MyHDL distribution. If they are installed in the typical way, they
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are therefore readily available for conversion verification.
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We will illustrate the registration process by showing the
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registrations of these simulators.
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GHDL registration::
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registerSimulator(
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name="GHDL",
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hdl="VHDL",
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analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
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elaborate="ghdl -e --workdir=work -o %(unitname)s_ghdl %(topname)s",
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simulate="ghdl -r %(unitname)s_ghdl"
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)
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registerSimulator(name="GHDL",
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analyze="ghdl -a --workdir=work %(topname)s.vhd",
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elaborate="ghdl -e --workdir=work %(topname)s",
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simulate="ghdl -r %(topname)s")
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Icarus registration::
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This assumes that the GHDL simulator is properly set up.
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registerSimulator(
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name="icarus",
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hdl="Verilog",
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analyze="iverilog -o %(topname)s.o %(topname)s.v",
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simulate="vvp %(topname)s.o"
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)
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cver registration::
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registerSimulator(
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name="cver",
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hdl="Verilog",
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analyze="cver -c -q %(topname)s.v",
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simulate="cver -q %(topname)s.v",
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offset=3
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)
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New modeling features
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@ -551,7 +581,7 @@ Backwards incompatible changes
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==============================
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.. _new-deco:
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.. _new06-deco:
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Decorator usage
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---------------
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@ -580,7 +610,7 @@ instances() function
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The :func:`instances()` function can be used to automatically lookup and
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return the instances that are defined in a MyHDL module. In accordance
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with the section :ref:`new-deco`, its functionality has been
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with the section :ref:`new06-deco`, its functionality has been
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changed. Only generators created by decorators are considered when
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looking up instances.
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@ -37,30 +37,28 @@ def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulat
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_simulateCommands[name] = simulate
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_offsets[name] = offset
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registerSimulator(name="GHDL",
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hdl="VHDL",
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analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
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elaborate="ghdl -e --workdir=work -o %(unitname)s_ghdl %(topname)s",
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simulate="ghdl -r %(unitname)s_ghdl"
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)
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registerSimulator(
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name="GHDL",
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hdl="VHDL",
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analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
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elaborate="ghdl -e --workdir=work -o %(unitname)s_ghdl %(topname)s",
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simulate="ghdl -r %(unitname)s_ghdl"
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)
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## registerSimulator(name="GHDL",
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## hdl="VHDL",
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## analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
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## elaborate="ghdl -e --workdir=work %(topname)s",
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## simulate="ghdl -r %(topname)s"
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## )
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registerSimulator(
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name="icarus",
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hdl="Verilog",
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analyze="iverilog -o %(topname)s.o %(topname)s.v",
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simulate="vvp %(topname)s.o"
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)
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registerSimulator(name="icarus",
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hdl="Verilog",
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analyze="iverilog -o %(topname)s.o %(topname)s.v",
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simulate="vvp %(topname)s.o")
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registerSimulator(name="cver",
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hdl="Verilog",
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analyze="cver -c -q %(topname)s.v",
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simulate="cver -q %(topname)s.v",
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offset=3)
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registerSimulator(
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name="cver",
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hdl="Verilog",
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analyze="cver -c -q %(topname)s.v",
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simulate="cver -q %(topname)s.v",
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offset=3
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)
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class _VerificationClass(object):
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