__vhdl__

myhdl/conversion/_analyze.py

@@ -475,9 +475,9 @@ class _AnalyzeVisitor(_ConversionMixin):
 
     def visitAssName(self, node, *args):
         n = node.name
-        if n ==  "__verilog__":
+        if n in ("__verilog__", "__vhdl__"):
             self.raiseError(node, _error.NotSupported,
-                            "__verilog__ in generator function")
+                            "%s in generator function" % n)
         # XXX ?
         if n in self.globalRefs:
             self.raiseError(node, _error.UnboundLocal, n)

myhdl/test/conversion/Makefile

@@ -0,0 +1,13 @@
+all: GHDL cver icarus
+
+GHDL:
+	py.test GHDL.py test_*.py
+
+icarus:
+	py.test icarus.py test_*.py
+
+cver:
+	py.test cver.py test_*.py
+
+clean:
+	- rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* *.log