diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 83cf4493..a83d2d1e 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -1117,7 +1117,6 @@ class _ConvertVisitor(_ConversionMixin): ## self.handlePrint(node) def visitPrintnl(self, node, *args): - print node.format ## self.handlePrint(node) argnr = 0 for s in node.format: @@ -1126,7 +1125,6 @@ class _ConvertVisitor(_ConversionMixin): else: a = node.args[argnr] argnr += 1 - print s.conv if s.conv is int: a.vhd = vhd_int() else: @@ -1267,6 +1265,7 @@ class _ConvertVisitor(_ConversionMixin): self.raiseError(node, "base type error in sensitivity list") if len(senslist) >= 2 and bt == _WaiterList: # ifnode = node.code.nodes[0] + # print ifnode assert isinstance(ifnode, astNode.If) asyncEdges = [] for test, suite in ifnode.tests: @@ -1411,7 +1410,7 @@ class _ConvertAlwaysDecoVisitor(_ConvertVisitor): def visitFunction(self, node, *args): assert self.ast.senslist senslist = self.ast.senslist - senslist = self.manageEdges(node.code.nodes[0], senslist) + senslist = self.manageEdges(node.code.nodes[-1], senslist) singleEdge = (len(senslist) == 1) and isinstance(senslist[0], _WaiterList) self.write("%s: process (" % self.ast.name) if singleEdge: @@ -1421,10 +1420,10 @@ class _ConvertAlwaysDecoVisitor(_ConvertVisitor): self.write(e) self.write(', ') self.write(senslist[-1]) + self.write(") is") self.indent() self.writeDeclarations() self.dedent() - self.write(") is") self.writeline() self.write("begin") self.indent() diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 9a654609..84d4b531 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -545,6 +545,9 @@ class _ConvertVisitor(_ConversionMixin): self.write(f.__name__) elif f is concat: opening, closing = '{', '}' + elif f is delay: + self.visit(node.args[0]) + return elif hasattr(node, 'ast'): self.write(node.ast.name) else: @@ -793,26 +796,60 @@ class _ConvertVisitor(_ConversionMixin): def visitPass(self, node, *args): self.write("// pass") - def handlePrint(self, node): - self.write('$display(') - s = node.nodes[0] - self.visit(s, _context.PRINT) - for s in node.nodes[1:]: - self.write(', , ') - self.visit(s, _context.PRINT) - self.write(');') +## def handlePrint(self, node): +## self.write('$display(') +## s = node.nodes[0] +## self.visit(s, _context.PRINT) +## for s in node.nodes[1:]: +## self.write(', , ') +## self.visit(s, _context.PRINT) +## self.write(');') - def visitPrint(self, node, *args): - self.handlePrint(node) +## def visitPrint(self, node, *args): +## self.handlePrint(node) def visitPrintnl(self, node, *args): - self.handlePrint(node) + argnr = 0 + for s in node.format: + if isinstance(s, str): + self.write('write(L, string\'("%s"));' % s) + else: + a = node.args[argnr] + argnr += 1 + obj = a.obj + if (s.conv is str) and isinstance(obj, bool): + w = 5 + else: + w = len(obj) + if s.width > w: + self.write('$write(" ";' % (s.width-w)) + self.writeline() + fs = "%d" + else: + fs = "%0d" + if (s.conv is str) and isinstance(obj, bool): + self.write('if (') + self.visit(a, _context.PRINT) + self.write(')') + self.writeline() + self.write(' $write(" True");') + self.writeline() + self.write('else') + self.writeline() + self.write(' $write("False");') + else: + self.write('$write("%s", ' % fs) + self.visit(a, _context.PRINT) + self.write(');') + self.writeline() + self.write('$write("\\n");') + def visitRaise(self, node, *args): - self.write('$display("') - self.visit(node.expr1) - self.write('");') - self.writeline() +## self.write('$display("') +## self.visit(node.expr1) +## self.write('");') +## self.writeline() self.write("$finish;") def visitReturn(self, node, *args): @@ -901,9 +938,16 @@ class _ConvertVisitor(_ConversionMixin): self.labelStack.pop() def visitYield(self, node, *args): - self.write("@ (") + yieldObj = self.getObj(node.value) + if isinstance(yieldObj, delay): + self.write("# ") + else: + self.write("@ (") self.visit(node.value, _context.YIELD) - self.write(");") + if isinstance(yieldObj, delay): + self.write(";") + else: + self.write(");") class _ConvertAlwaysVisitor(_ConvertVisitor): diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py index 818bb18f..95ce5889 100644 --- a/myhdl/conversion/_verify.py +++ b/myhdl/conversion/_verify.py @@ -11,16 +11,17 @@ from myhdl.conversion._toVerilog import toVerilog _version = myhdl.__version__.replace('.','') _simulators = [] -_conversionCommands = {} +_hdlMap = {} _analyzeCommands = {} _elaborateCommands = {} _simulateCommands = {} +_offsets = {} -def registerSimulator(name=None, convert=None, analyze=None, elaborate=None, simulate=None): +def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulate=None, offset=0): if not isinstance(name, str) or (name.strip() == ""): raise ValueError("Invalid simulator name") - if convert not in (toVHDL, toVerilog): - raise ValueError("Invalid convert command") + if hdl not in ("VHDL", "Verilog"): + raise ValueError("Invalid hdl %s" % hdl) if not isinstance(analyze, str) or (analyze.strip() == ""): raise ValueError("Invalid analyzer command") # elaborate command is optional @@ -30,21 +31,28 @@ def registerSimulator(name=None, convert=None, analyze=None, elaborate=None, sim if not isinstance(simulate, str) or (simulate.strip() == ""): raise ValueError("Invalid simulator command") _simulators.append(name) - _conversionCommands[name] = convert + _hdlMap[name] = hdl _analyzeCommands[name] = analyze _elaborateCommands[name] = elaborate _simulateCommands[name] = simulate + _offsets[name] = offset registerSimulator(name="GHDL", - convert=toVHDL, + hdl="VHDL", analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd", elaborate="ghdl -e --workdir=work %(topname)s", simulate="ghdl -r %(topname)s") registerSimulator(name="icarus", - convert=toVerilog, + hdl="Verilog", analyze="iverilog -o %(topname)s.o %(topname)s.v", simulate="vvp %(topname)s.o") + +registerSimulator(name="cver", + hdl="Verilog", + analyze="cver -c -q %(topname)s.v", + simulate="cver -q %(topname)s.v", + offset=3) class _VerificationClass(object): @@ -62,21 +70,25 @@ class _VerificationClass(object): vals['topname'] = func.func_name vals['version'] = _version - hdl = self.simulator - if not hdl: + hdlsim = self.simulator + if not hdlsim: raise ValueError("No simulator specified") - if not hdl in _simulators: - raise ValueError("Simulator %s is not registered" % hdl) - convert = _conversionCommands[hdl] - analyze = _analyzeCommands[hdl] % vals - elaborate = _elaborateCommands[hdl] + if not hdlsim in _simulators: + raise ValueError("Simulator %s is not registered" % hdlsim) + hdl = _hdlMap[hdlsim] + analyze = _analyzeCommands[hdlsim] % vals + elaborate = _elaborateCommands[hdlsim] if elaborate is not None: elaborate = elaborate % vals - simulate = _simulateCommands[hdl] % vals - - inst = convert(func, *args, **kwargs) + simulate = _simulateCommands[hdlsim] % vals + offset = _offsets[hdlsim] - if convert is toVHDL: + if hdl == "VHDL": + inst = toVHDL(func, *args, **kwargs) + else: + inst = toVerilog(func, *args, **kwargs) + + if hdl == "VHDL": if not os.path.exists("work"): os.mkdir("work") ret = subprocess.call(analyze, shell=True) @@ -117,13 +129,13 @@ class _VerificationClass(object): g.flush() g.seek(0) - glines = g.readlines() + glines = g.readlines()[offset:] flinesNorm = [line.lower() for line in flines] glinesNorm = [line.lower() for line in glines] - g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile=hdl, tofile="VHDL") + g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile=hdlsim, tofile=hdl) MyHDLLog = "MyHDL.log" - HDLLog = hdl + ".log" + HDLLog = hdlsim + ".log" try: os.remove(MyHDLLog) os.remove(HDLLog)