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clarified synthesis

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Jan Decaluwe 2012-05-06 14:59:24 +02:00
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6
doc/source/manual/conversion.rst
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@ -35,9 +35,9 @@ or VHDL, using the function :func:`toVerilog` or :func:`toVHDL` from the MyHDL
library. library.
When the design is intended for implementation When the design is intended for implementation
a third-party :dfn:`synthesis tool` is used to convert the Verilog or VHDL a third-party :dfn:`synthesis tool` is used to compile the Verilog or VHDL
design to a gate implementation for an ASIC or FPGA. With this step, there is model into an implementation for an ASIC or FPGA. With this step, there is
a path from a hardware description in Python to an FPGA or ASIC implementation. an automated path from a hardware description in Python to an FPGA or ASIC implementation.
The conversion does not start from source files, but from an instantiated design The conversion does not start from source files, but from an instantiated design
that has been *elaborated* by the Python interpreter. The converter uses the that has been *elaborated* by the Python interpreter. The converter uses the

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doc/source/manual/rtl.rst
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@ -14,6 +14,8 @@ Introduction
RTL (Register Transfer Level) is a modeling abstraction level that RTL (Register Transfer Level) is a modeling abstraction level that
is typically used to write synthesizable models. is typically used to write synthesizable models.
:dfn:`Synthesis` refers to the process by which an HDL description
is automatically compiled into an implementation for an ASIC or FPGA.
This chapter describes how MyHDL supports it. This chapter describes how MyHDL supports it.