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Solved bug in always_seq conversion to Verilog

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--HG--
branch : 0.8-dev
This commit is contained in:
Jan Decaluwe 2012-08-28 10:59:51 +02:00
parent 64b9f4d359
commit 951d0d53ae
1 changed files with 5 additions and 1 deletions
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6
myhdl/conversion/_toVerilog.py
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@ -1347,10 +1347,14 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor):
self.writeline()
self.write("end")
self.writeline()
self.write("else")
self.write("else begin")
self.indent()
self.visit_stmt(node.body)
self.dedent()
if reset is not None:
self.writeline()
self.write("end")
self.dedent()
self.writeline()
self.write("end")
self.writeline(2)