From 951d0d53ae636894a21b278c1ed9cef05390d90f Mon Sep 17 00:00:00 2001 From: Jan Decaluwe Date: Tue, 28 Aug 2012 10:59:51 +0200 Subject: [PATCH] Solved bug in always_seq conversion to Verilog --HG-- branch : 0.8-dev --- myhdl/conversion/_toVerilog.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 2963d736..8761c4a7 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -1347,10 +1347,14 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor): self.writeline() self.write("end") self.writeline() - self.write("else") + self.write("else begin") self.indent() self.visit_stmt(node.body) self.dedent() + if reset is not None: + self.writeline() + self.write("end") + self.dedent() self.writeline() self.write("end") self.writeline(2)