FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

docstrings in Verilog output

Browse Source
This commit is contained in:
Jan Decaluwe 2010-06-22 13:28:51 +02:00
parent 1ab5fccce8
commit 96ad4abbcd
1 changed files with 23 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
myhdl/conversion/_toVerilog.py
View File

@ -71,7 +71,17 @@ def _flatten(*args):
else:
arglist.append(arg)
return arglist
def _makeDoc(doc, indent=''):
if doc is None:
return ''
pre = indent + '// '
doc = pre + doc
pre = '\n' + pre
doc = doc.replace('\n', pre)
doc = doc + '\n'
return doc
class _ToVerilogConvertor(object):
@ -127,9 +137,10 @@ class _ToVerilogConvertor(object):
genlist = _analyzeGens(arglist, h.absnames)
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
doc = _makeDoc(inspect.getdoc(func))
_writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf)
_writeModuleHeader(vfile, intf, doc)
_writeSigDecls(vfile, intf, siglist, memlist)
_convertGens(genlist, vfile)
_writeModuleFooter(vfile)
@ -182,7 +193,7 @@ def _writeFileHeader(f, fn, ts):
print >> f
def _writeModuleHeader(f, intf):
def _writeModuleHeader(f, intf, doc):
print >> f, "module %s (" % intf.name
b = StringIO()
for portname in intf.argnames:
@ -190,6 +201,7 @@ def _writeModuleHeader(f, intf):
print >> f, b.getvalue()[:-2]
b.close()
print >> f, ");"
print >> f, doc
print >> f
for portname in intf.argnames:
s = intf.argdict[portname]
@ -402,6 +414,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
for i in range(nr):
self.buf.write("\n%s" % self.ind)
def writeDoc(self, node):
doc = ast.get_docstring(node)
doc = _makeDoc(doc)
self.write(doc)
def indent(self):
self.ind += ' ' * 4
@ -1827,6 +1844,7 @@ class _ConvertAlwaysCombVisitor(_ConvertVisitor):
def visit_FunctionDef(self, node):
self.writeDoc(node)
self.writeAlwaysHeader()
self.writeDeclarations()
self.visit_stmt(node.body)
@ -1860,6 +1878,7 @@ class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor):
# self.writeline(2)
def visit_FunctionDef(self, node):
self.writeDoc(node)
self.visit_stmt(node.body)
self.writeline(2)
@ -1884,6 +1903,7 @@ class _ConvertAlwaysDecoVisitor(_ConvertVisitor):
# self.writeline(2)
def visit_FunctionDef(self, node):
self.writeDoc(node)
self.writeAlwaysHeader()
self.writeDeclarations()
self.visit_stmt(node.body)