From 982ba812f8efc4dbcf1ed748cca3f02051f29c2b Mon Sep 17 00:00:00 2001 From: jand Date: Wed, 29 Oct 2003 15:53:39 +0000 Subject: [PATCH] error handling --- myhdl/_Cosimulation.py | 19 ++++++++++--------- myhdl/_Simulation.py | 11 +---------- myhdl/_always_comb.py | 11 +---------- myhdl/_extractHierarchy.py | 11 +---------- myhdl/_toVerilog.py | 14 +++----------- myhdl/_traceSignals.py | 10 +--------- myhdl/_util.py | 1 - myhdl/test/test_traceSignals.py | 1 - myhdl/test/toVerilog/test_bin2gray.py | 3 ++- 9 files changed, 19 insertions(+), 62 deletions(-) diff --git a/myhdl/_Cosimulation.py b/myhdl/_Cosimulation.py index 9e367f2d..f797a1be 100644 --- a/myhdl/_Cosimulation.py +++ b/myhdl/_Cosimulation.py @@ -30,18 +30,19 @@ import exceptions from myhdl._intbv import intbv from myhdl import _simulator +from myhdl._Error import Error _MAXLINE = 4096 -class Error(Exception): - """Cosimulation Error""" - def __init__(self, arg=""): - self.arg = arg - def __str__(self): - msg = self.__doc__ - if self.arg: - msg = msg + ": " + str(self.arg) - return msg +## class Error(Exception): +## """Cosimulation Error""" +## def __init__(self, arg=""): +## self.arg = arg +## def __str__(self): +## msg = self.__doc__ +## if self.arg: +## msg = msg + ": " + str(self.arg) +## return msg class MultipleCosimError(Error): """Only a single cosimulator allowed""" diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py index 0745c06b..b742fa70 100644 --- a/myhdl/_Simulation.py +++ b/myhdl/_Simulation.py @@ -34,20 +34,11 @@ from myhdl import _simulator from myhdl._simulator import _siglist, _futureEvents from myhdl._Waiter import _Waiter, _WaiterList from myhdl._util import StopSimulation, SuspendSimulation +from myhdl._Error import Error schedule = _futureEvents.append -class Error(Exception): - """Simulation Error""" - def __init__(self, arg=""): - self.arg = arg - def __str__(self): - msg = self.__doc__ - if self.arg: - msg = msg + ": " + str(self.arg) - return msg - class MultipleCosimError(Error): """Only a single cosimulator argument allowed""" class ArgTypeError(Error): diff --git a/myhdl/_always_comb.py b/myhdl/_always_comb.py index 7f50b453..b24daa50 100644 --- a/myhdl/_always_comb.py +++ b/myhdl/_always_comb.py @@ -33,16 +33,7 @@ from sets import Set from myhdl import Signal from myhdl._util import _isGenFunc - -class Error(Exception): - """always_comb Error""" - def __init__(self, arg=""): - self.arg = arg - def __str__(self): - msg = self.__doc__ - if self.arg: - msg = msg + ": " + str(self.arg) - return msg +from myhdl._Error import Error class ArgumentError(Error): """ always_comb argument should be a classic function""" diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py index 115bd1bb..97999ad6 100644 --- a/myhdl/_extractHierarchy.py +++ b/myhdl/_extractHierarchy.py @@ -39,19 +39,10 @@ from sets import Set from myhdl import Signal from myhdl._util import _isGenSeq, _isGenFunc +from myhdl._Error import Error _profileFunc = None - -class Error(Exception): - """ traceSignals Error""" - def __init__(self, arg=""): - self.arg = arg - def __str__(self): - msg = self.__doc__ - if self.arg: - msg = msg + ": " + str(self.arg) - return msg class NoInstancesError(Error): """No instances found""" diff --git a/myhdl/_toVerilog.py b/myhdl/_toVerilog.py index 8d57035d..8a3b3ea6 100644 --- a/myhdl/_toVerilog.py +++ b/myhdl/_toVerilog.py @@ -35,6 +35,7 @@ from cStringIO import StringIO from myhdl import Signal, intbv from myhdl._extractHierarchy import _HierExtr, _findInstanceName +from myhdl._Error import Error def _flatten(*args): @@ -52,16 +53,6 @@ def _flatten(*args): _converting = 0 _profileFunc = None -class Error(Exception): - """ toVerilog Error""" - def __init__(self, arg=""): - self.arg = arg - def __str__(self): - if self.__doc__ and self.arg: - msg = self.__doc__ + ": " + str(self.arg) - else: - msg = self.__doc__ or self.arg - return msg class TopLevelNameError(Error): """result of toVerilog call should be assigned to a top level name""" @@ -79,6 +70,7 @@ class UndrivenSignalError(Error): """Signal is not driven""" + def toVerilog(func, *args, **kwargs): global _converting if _converting: @@ -163,6 +155,7 @@ def _analyzeGens(top, gennames): gen.lineoffset = inspect.getsourcelines(f)[1]-1 symdict = f.f_globals.copy() symdict.update(f.f_locals) + print f.f_locals sigdict = {} for n, v in symdict.items(): if isinstance(v, Signal): @@ -318,7 +311,6 @@ class _AnalyzeGenVisitor(_ToVerilogBaseVisitor): def visitAssign(self, node, access=OUTPUT): for n in node.nodes: self.visit(n, OUTPUT) - print node.expr self.visit(node.expr, INPUT) diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py index d593406f..af82b5b7 100644 --- a/myhdl/_traceSignals.py +++ b/myhdl/_traceSignals.py @@ -35,19 +35,11 @@ from sets import Set from myhdl import _simulator, Signal, __version__ from myhdl._util import _isGenSeq, _isGenFunc from myhdl._extractHierarchy import _findInstanceName, _HierExtr +from myhdl._Error import Error _tracing = 0 _profileFunc = None -class Error(Exception): - """ traceSignals Error""" - def __init__(self, arg=""): - self.arg = arg - def __str__(self): - msg = self.__doc__ - if self.arg: - msg = msg + ": " + str(self.arg) - return msg class TopLevelNameError(Error): """result of traceSignals call should be assigned to a top level name""" diff --git a/myhdl/_util.py b/myhdl/_util.py index 4f346ecd..d597a850 100644 --- a/myhdl/_util.py +++ b/myhdl/_util.py @@ -21,7 +21,6 @@ This module provides the following myhdl objects: downrange -- function that returns a downward range -Error -- myhdl Error exception bin -- returns a binary string representation. The optional width specifies the desired string width: padding of the sign-bit is used. diff --git a/myhdl/test/test_traceSignals.py b/myhdl/test/test_traceSignals.py index 5c79028a..5a1bc858 100644 --- a/myhdl/test/test_traceSignals.py +++ b/myhdl/test/test_traceSignals.py @@ -120,7 +120,6 @@ class TestTraceSigs(TestCase): else: self.fail() - def testReturnVal(self): try: dut = traceSignals(dummy) diff --git a/myhdl/test/toVerilog/test_bin2gray.py b/myhdl/test/toVerilog/test_bin2gray.py index 47db62af..bc9e4c53 100644 --- a/myhdl/test/toVerilog/test_bin2gray.py +++ b/myhdl/test/toVerilog/test_bin2gray.py @@ -14,8 +14,9 @@ def bin2gray(B, G, width): """ while 1: yield B + # a = 3 for i in range(width): - G.next[i] = B[i] ^ B[i] + G.next[i] = B[i+1] ^ B[i] analyze_cmd = "iverilog -o bin2gray bin2gray_1.v tb_bin2gray_1.v"