FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

and continuing

Browse Source
This commit is contained in:
Josy Boelen 2021-03-06 20:07:55 +01:00
parent 493a7e90d8
commit 989be768a4
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
myhdl/conversion/_toVHDL.py
View File

@ -1251,6 +1251,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.write("to_signed(%s, %s)" % (n, node.vhd.size)) self.write("to_signed(%s, %s)" % (n, node.vhd.size))
else: else:
self.write('signed\'("%s")' % tobin(n, node.vhd.size)) self.write('signed\'("%s")' % tobin(n, node.vhd.size))
else: else:
if n < 0: if n < 0:
self.write("(") self.write("(")