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mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00

move to 0.6dev4

fix custom Verilog test
This commit is contained in:
jand 2007-01-12 21:37:43 +00:00
parent f1056327bd
commit 9b92962595
6 changed files with 8 additions and 8 deletions

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@ -1,4 +1,4 @@
Release 0.6dev3
Release 0.6dev4
---------------
Release 0.5.1 1-May-2006

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@ -1,4 +1,4 @@
MyHDL Release 0.6dev3
MyHDL Release 0.6dev4
=====================
OVERVIEW

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@ -142,8 +142,8 @@ class _HierExtr(object):
def __init__(self, name, dut, *args, **kwargs):
global _profileFunc
global _memInfoMap
_memInfoMap = {}
_memInfoMap.clear()
_userDefinedVerilogMap.clear()
self.skipNames = ('always_comb', 'always', '_always_decorator', 'instance', \
'instances', 'processes', 'posedge', 'negedge')
self.skip = 0

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@ -30,14 +30,14 @@ import test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
test_inc_initial, test_hec, test_loops, test_infer, test_errors, \
test_RandomScrambler, test_beh, test_GrayInc, test_misc, \
test_ram, test_rom, test_always_comb, test_dec, test_signed, \
test_edge
test_edge, test_custom
modules = (test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
test_inc_initial, test_hec, test_loops, test_infer, test_errors, \
test_RandomScrambler, test_beh, test_GrayInc, test_misc, \
test_ram, test_rom, test_always_comb, test_dec, test_signed, \
test_edge
test_edge, test_custom
)

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@ -11,7 +11,7 @@ from myhdl import *
from util import setupCosimulation
from myhdl import ConversionError
from myhdl._toVerilog import _error
from myhdl.conversion._misc import _error
ACTIVE_LOW, INACTIVE_HIGH = 0, 1

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@ -32,7 +32,7 @@ Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
setup(name="myhdl",
version="0.6dev3",
version="0.6dev4",
description="Python as a Hardware Description Language",
long_description = "See home page.",
author="Jan Decaluwe",