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move to 0.6dev4
fix custom Verilog test
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@ -1,4 +1,4 @@
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Release 0.6dev3
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Release 0.6dev4
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---------------
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Release 0.5.1 1-May-2006
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@ -1,4 +1,4 @@
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MyHDL Release 0.6dev3
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MyHDL Release 0.6dev4
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=====================
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OVERVIEW
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@ -142,8 +142,8 @@ class _HierExtr(object):
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def __init__(self, name, dut, *args, **kwargs):
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global _profileFunc
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global _memInfoMap
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_memInfoMap = {}
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_memInfoMap.clear()
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_userDefinedVerilogMap.clear()
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self.skipNames = ('always_comb', 'always', '_always_decorator', 'instance', \
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'instances', 'processes', 'posedge', 'negedge')
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self.skip = 0
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@ -30,14 +30,14 @@ import test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
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test_inc_initial, test_hec, test_loops, test_infer, test_errors, \
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test_RandomScrambler, test_beh, test_GrayInc, test_misc, \
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test_ram, test_rom, test_always_comb, test_dec, test_signed, \
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test_edge
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test_edge, test_custom
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modules = (test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
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test_inc_initial, test_hec, test_loops, test_infer, test_errors, \
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test_RandomScrambler, test_beh, test_GrayInc, test_misc, \
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test_ram, test_rom, test_always_comb, test_dec, test_signed, \
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test_edge
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test_edge, test_custom
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)
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@ -11,7 +11,7 @@ from myhdl import *
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from util import setupCosimulation
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from myhdl import ConversionError
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from myhdl._toVerilog import _error
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from myhdl.conversion._misc import _error
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ACTIVE_LOW, INACTIVE_HIGH = 0, 1
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