diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py
index ee90efeb..f96851a5 100644
--- a/myhdl/_extractHierarchy.py
+++ b/myhdl/_extractHierarchy.py
@@ -96,7 +96,7 @@ class _UserCode(object):
 
     def __str__(self):
         try:
-            code = self.code % self.namespace
+            code =  self._interpolate()
         except:
             type, value, tb = sys.exc_info()
             info = "in file %s, function %s starting on line %s:\n    " % \
@@ -105,6 +105,13 @@ class _UserCode(object):
             self.raiseError(msg, info)
         code = "\n%s\n" % code
         return code
+    
+    def _interpolate(self):
+        return string.Template(self.code).substitute(self.namespace)
+    
+class _UserCodeDepr(_UserCode):
+    def _interpolate(self):
+        return self.code % self.namespace
 
 class _UserVerilogCode(_UserCode):
     def raiseError(self, msg, info):
@@ -114,6 +121,13 @@ class _UserVhdlCode(_UserCode):
     def raiseError(self, msg, info):
         raise ToVHDLError("Error in user defined VHDL code", msg, info)
     
+class _UserVerilogCodeDepr(_UserVerilogCode, _UserCodeDepr):
+    pass
+
+class _UserVhdlCodeDepr(_UserVhdlCode, _UserCodeDepr):
+    pass
+     
+    
 class _UserVerilogInstance(_UserVerilogCode):
     def __str__(self):
         args = inspect.getargspec(self.func)[0]
@@ -147,8 +161,8 @@ class _UserVhdlInstance(_UserVhdlCode):
 
 def _addUserCode(specs, arg, funcname, func, frame):
     classMap = {
-                '__verilog__' : _UserVerilogCode,
-                '__vhdl__' :_UserVhdlCode,
+                '__verilog__' : _UserVerilogCodeDepr,
+                '__vhdl__' :_UserVhdlCodeDepr,
                 'verilog_code' : _UserVerilogCode,
                 'vhdl_code' :_UserVhdlCode,
                 'verilog_instance' : _UserVerilogInstance,
diff --git a/myhdl/test/conversion/toVHDL/test_newcustom.py b/myhdl/test/conversion/toVHDL/test_newcustom.py
index de18f3ce..c7e6db1d 100644
--- a/myhdl/test/conversion/toVHDL/test_newcustom.py
+++ b/myhdl/test/conversion/toVHDL/test_newcustom.py
@@ -72,12 +72,12 @@ def inc(count, enable, clock, reset, n):
 
     inc.vhdl_code = \
 """
-process (%(clock)s, %(reset)s) begin
+process ($clock, $reset) begin
     if (reset = '0') then
-        %(count)s <= (others => '0');
-    elsif rising_edge(%(clock)s) then
+        $count <= (others => '0');
+    elsif rising_edge($clock) then
         if (enable = '1') then
-            %(count)s <= (%(count)s + 1) mod %(n)s;
+            $count <= ($count + 1) mod $n;
         end if;
     end if;
 end process;
@@ -102,13 +102,13 @@ def incErr(count, enable, clock, reset, n):
 
     incErr.vhdl_code = \
 """
-always @(posedge %(clock)s, negedge %(reset)s) begin
+always @(posedge $clock, negedge $reset) begin
     if (reset == 0) begin
-        %(count)s <= 0;
+        $count <= 0;
     end
     else begin
         if (enable) begin
-            %(count)s <= (%(countq)s + 1) %% %(n)s;
+            $count <= ($countq + 1) %% $n;
         end
     end
 end
@@ -130,7 +130,7 @@ def inc_comb(nextCount, count, n):
 
     inc_comb.vhdl_code =\
 """
-%(nextCount)s <= (%(count)s + 1) mod %(n)s;
+$nextCount <= ($count + 1) mod $n;
 """
 
     return logic
@@ -149,12 +149,12 @@ def inc_seq(count, nextCount, enable, clock, reset):
 
     inc_seq.vhdl_code = \
 """
-process (%(clock)s, %(reset)s) begin
+process ($clock, $reset) begin
     if (reset = '0') then
-        %(count)s <= (others => '0');
-    elsif rising_edge(%(clock)s) then
+        $count <= (others => '0');
+    elsif rising_edge($clock) then
         if (enable = '1') then
-            %(count)s <= %(nextCount)s;
+            $count <= $nextCount;
         end if;
     end if;
 end process;
diff --git a/myhdl/test/conversion/toVerilog/test_newcustom.py b/myhdl/test/conversion/toVerilog/test_newcustom.py
index b976f205..a22204ad 100644
--- a/myhdl/test/conversion/toVerilog/test_newcustom.py
+++ b/myhdl/test/conversion/toVerilog/test_newcustom.py
@@ -41,7 +41,7 @@ def incGen(count, enable, clock, reset, n):
     """ Generator with __verilog__ is not permitted """
     @instance
     def logic():
-        __verilog__ = "Template string"
+        incGen.verilog_code = "Template string"
         while 1:
                 yield clock.posedge, reset.negedge
                 if reset == ACTIVE_LOW:
@@ -75,13 +75,13 @@ def inc(count, enable, clock, reset, n):
 
     inc.verilog_code = \
 """
-always @(posedge %(clock)s, negedge %(reset)s) begin
+always @(posedge $clock, negedge $reset) begin
     if (reset == 0) begin
-        %(count)s <= 0;
+        $count <= 0;
     end
     else begin
         if (enable) begin
-            %(count)s <= (%(count)s + 1) %% %(n)s;
+            $count <= ($count + 1) % $n;
         end
     end
 end
@@ -106,13 +106,13 @@ def incErr(count, enable, clock, reset, n):
 
     incErr.verilog_code = \
 """
-always @(posedge %(clock)s, negedge %(reset)s) begin
+always @(posedge $clock, negedge $reset) begin
     if (reset == 0) begin
-        %(count)s <= 0;
+        $count <= 0;
     end
     else begin
         if (enable) begin
-            %(count)s <= (%(countq)s + 1) %% %(n)s;
+            $count <= ($countq + 1) % $n;
         end
     end
 end
@@ -134,7 +134,7 @@ def inc_comb(nextCount, count, n):
 
     inc_comb.verilog_code =\
 """
-assign %(nextCount)s = (%(count)s + 1) %% %(n)s;
+assign $nextCount = ($count + 1) % $n;
 """
 
     return logic
@@ -153,13 +153,13 @@ def inc_seq(count, nextCount, enable, clock, reset):
 
     inc_seq.verilog_code = \
 """
-always @(posedge %(clock)s, negedge %(reset)s) begin
+always @(posedge $clock, negedge $reset) begin
     if (reset == 0) begin
-        %(count)s <= 0;
+        $count <= 0;
     end
     else begin
         if (enable) begin
-            %(count)s <= %(nextCount)s;
+            $count <= $nextCount;
         end
     end
 end