From ff5b0b1963505b90430d7cd72a06c50c3a1a15c0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Pierre=20Clad=C3=A9?= <pierre.clade@spectro.jussieu.fr>
Date: Thu, 29 Oct 2015 19:03:14 +0100
Subject: [PATCH] assign statement (constwires) support litterals larger than
 32 bits

---
 myhdl/conversion/_toVerilog.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
index 6d5786cd..4139e3ba 100644
--- a/myhdl/conversion/_toVerilog.py
+++ b/myhdl/conversion/_toVerilog.py
@@ -324,7 +324,9 @@ def _writeSigDecls(f, intf, siglist, memlist):
             c = int(s.val)
         else:
             raise ToVerilogError("Unexpected type for constant signal", s._name)
-        print("assign %s = %s;" % (s._name, c), file=f)
+        c_len = s._nrbits
+        c_str = "%s"%c
+        print("assign %s = %s'd%s;" % (s._name, c_len,  c_str), file=f)
     print(file=f)
     # shadow signal assignments
     for s in siglist: