added draft implementation of modbv.py and corresponding benchmark updates

--HG--
branch : 0.8-dev

CHANGES.txt

@@ -1,5 +1,5 @@
-0.8-dev
--------
+0.8dev
+------
 
 Release 0.7 24-Dec-2010
 -----------------------

README.txt

@@ -1,5 +1,5 @@
-MyHDL 0.7
-=========
+MyHDL 0.8dev
+============
 
 What is MyHDL?
 --------------

myhdl/__init__.py

@@ -32,6 +32,7 @@ posedge -- callable to model a rising edge on a signal in a yield statement
 negedge -- callable to model a falling edge on a signal in a yield statement
 join -- callable to join clauses in a yield statement
 intbv -- mutable integer class with bit vector facilities
+modbv -- modular bit vector class
 downrange -- function that returns a downward range
 bin -- returns a binary string representation.
        The optional width specifies the desired string
@@ -46,7 +47,7 @@ toVerilog -- function that converts a design to Verilog
 
 """
 
-__version__ = "0.8-dev"
+__version__ = "0.8dev"
 
 import sys
 import warnings
@@ -110,6 +111,7 @@ warnings.showwarning = showwarning
 from _bin import bin
 from _concat import concat
 from _intbv import intbv
+from _modbv import modbv
 from _join import join
 from _Signal import posedge, negedge, Signal, SignalType
 from _ShadowSignal import ConcatSignal
@@ -135,6 +137,7 @@ from _tristate import Tristate
 __all__ = ["bin",
            "concat",
            "intbv",
+           "modbv",
            "join",
            "posedge",
            "negedge",

myhdl/_intbv.py

@@ -31,7 +31,7 @@ from myhdl._bin import bin
 from __builtin__ import max as maxfunc
 
 class intbv(object):
-    __slots__ = ('_val', '_min', '_max', '_nrbits')
+    __slots__ = ('_val', '_min', '_max', '_nrbits', '_handleBounds')
     
     def __init__(self, val=0, min=None, max=None, _nrbits=0):
         if _nrbits:

myhdl/_modbv.py

@@ -0,0 +1,31 @@
+#  This file is part of the myhdl library, a Python package for using
+#  Python as a Hardware Description Language.
+#
+#  Copyright (C) 2003-2011 Jan Decaluwe
+#
+#  The myhdl library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public License as
+#  published by the Free Software Foundation; either version 2.1 of the
+#  License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  Lesser General Public License for more details.
+
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+""" Module with the modbv class """
+
+from _intbv import intbv
+
+class modbv(intbv):
+    __slots__ = []
+
+    def _handleBounds(self):
+        lo, hi = self._min, self._max
+        if lo is None or hi is None:
+           return
+        self._val = (self._val - lo) % (hi - lo) + lo

myhdl/test/benchmark/lfsr24.py

@@ -9,7 +9,7 @@ def lfsr24(lfsr, enable, clock, reset):
         else:
             if enable:
                 # lfsr.next[24:1] = lfsr[23:0]
-                lfsr.next = lfsr[23:0] << 1
+                lfsr.next = lfsr << 1
                 lfsr.next[0] = lfsr[23] ^ lfsr[22] ^ lfsr[21] ^ lfsr[16]
 
     return logic

myhdl/test/benchmark/pypyrun.sh

@@ -0,0 +1,28 @@
+#!/bin/bash
+
+echo > pypystats.dat
+
+tests="
+timer
+lfsr24
+randgen
+longdiv
+findmax
+"
+
+for test in $tests
+do
+echo Test: $test >> pypystats.dat
+echo ===== >> pypystats.dat
+
+
+echo pypy >> pypystats.dat
+echo ---- >> pypystats.dat
+/usr/bin/time -o pypystats.dat -a -p pypy test_$test.py > ${test}_pypy.out
+echo >> pypystats.dat
+
+
+done
+
+
+

myhdl/test/benchmark/pypystats.dat

@@ -0,0 +1,41 @@
+
+Test: timer
+=====
+pypy
+----
+real 82.23
+user 81.90
+sys 0.14
+
+Test: lfsr24
+=====
+pypy
+----
+real 128.67
+user 128.26
+sys 0.11
+
+Test: randgen
+=====
+pypy
+----
+real 81.08
+user 80.73
+sys 0.16
+
+Test: longdiv
+=====
+pypy
+----
+real 102.89
+user 102.59
+sys 0.05
+
+Test: findmax
+=====
+pypy
+----
+real 140.60
+user 140.14
+sys 0.11
+

myhdl/test/benchmark/test_lfsr24.py

@@ -4,7 +4,8 @@ from lfsr24 import lfsr24
 
 def test_lfsr24():
 
-    lfsr = Signal(intbv(0)[24:])
+    #lfsr = Signal(modbv(0)[24:])
+    lfsr = Signal(modbv(0, min=0, max=2**24))
     enable = Signal(bool())
     clock = Signal(bool())
     reset = Signal(bool())

myhdl/test/benchmark/testrun.sh

@@ -4,12 +4,12 @@ echo > teststats.dat
 
 python convert.py
 
-ghdl -a pck_myhdl_07.vhd
+ghdl -a pck_myhdl_08dev.vhd
 vlib work
-vcom pck_myhdl_07.vhd
+vcom pck_myhdl_08dev.vhd
 
 tests="
-findmax
+lfsr24
 "
 
 for test in $tests

myhdl/test/benchmark/teststats.dat

@@ -0,0 +1,36 @@
+
+Test: lfsr24
+=====
+python
+------
+
+pypy
+----
+real 135.26
+user 134.76
+sys 0.18
+
+icarus
+------
+real 80.79
+user 80.36
+sys 0.26
+
+ghdl
+----
+real 71.13
+user 70.97
+sys 0.01
+
+vlog
+----
+real 266.11
+user 107.63
+sys 157.69
+
+vcom
+----
+real 240.08
+user 109.03
+sys 130.30
+

setup.py

@@ -32,7 +32,7 @@ Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
 
     
 setup(name="myhdl",
-      version="0.8-dev",
+      version="0.8dev",
       description="Python as a Hardware Description Language",
       long_description = "See home page.",
       author="Jan Decaluwe",