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https://github.com/myhdl/myhdl.git
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signed expressions
This commit is contained in:
jand
parent
c7fc9d7633
commit
a0289a4fe8
@ -171,13 +171,38 @@ def _writeModuleHeader(f, intf):
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funcdecls = """\
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function to_std_logic (arg : boolean) return std_logic is begin
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function to_std_logic (arg: boolean) return std_logic is
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begin
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if arg then
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return '1';
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else
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return '0';
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end if;
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end function to_std_logic;
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function to_unsigned (arg: boolean; size: natural) return unsigned is
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variable res: unsigned(size-1 downto 0) := (others => '0');
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begin
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if arg then
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res(0):= '1';
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end if;
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return res;
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end function to_unsigned;
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function to_signed (arg: boolean; size: natural) return signed is
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variable res: signed(size-1 downto 0) := (others => '0');
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begin
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if arg then
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res(0) := '1';
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end if;
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return res;
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end function to_signed;
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function "-" (arg: unsigned) return signed is
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begin
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return - signed(resize(arg, arg'length+1));
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end function "-";
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"""
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def _writeFuncDecls(f):
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@ -408,7 +433,7 @@ class _ConvertVisitor(_ConversionMixin):
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def binaryOp(self, node, op=None):
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n, o, l, r = node.vhd, node.vhdOri, node.left.vhd, node.right.vhd
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nc, rc, lc = self.inferBinaryOpCasts(node, n, o, l, r, op)
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nc, lc, rc = self.inferBinaryOpCasts(node, n, o, l, r, op)
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context = None
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self.write(nc.pre)
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self.write("(")
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@ -429,28 +454,30 @@ class _ConvertVisitor(_ConversionMixin):
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nc, lc, rc = [_Cast() for i in range(3)]
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if isinstance(o, vhd_int):
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if isinstance(n, vhd_unsigned):
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nc.pre, nc.suf = "to_unsigned(", ", %s)" % node.vhd.size
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nc.pre, nc.suf = "to_unsigned(", ", %s)" % ns
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elif isinstance(n, vhd_signed):
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nc.pre, nc.suf = "to_signed(", ", %s)" % node.vhd.size
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nc.pre, nc.suf = "to_signed(", ", %s)" % ns
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elif isinstance(n, vhd_int):
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pass
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else:
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self.raiseError(node, "Not implemented")
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elif isinstance(l, vhd_unsigned) and isinstance(r, (vhd_int, vhd_unsigned)):
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print "HERE1"
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print op
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elif isinstance(l, vhd_vector) and isinstance(r, (vhd_int, vhd_vector)):
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if ds < 0:
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nc.pre, nc.suf = "resize(", ", %s)" % ns
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elif ds > 0:
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print "HERE"
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print op
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if op in ('+', '-', '/'):
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lc.pre, lc.suf = "resize(", ", %s)" % ns
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elif op in ('mod', ):
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print 'MOD HERE'
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nc.pre, nc.suf = "resize(", ", %s)" % ns
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else:
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self.raiseError(node, "Not implemented")
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if isinstance(n, vhd_signed) and isinstance(o, vhd_unsigned):
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nc.pre = "signed(" + nc.pre
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nc.suf = nc.suf + ")"
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elif isinstance(n, vhd_unsigned) and isinstance(o, vhd_signed):
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nc.pre = "unsigned(" + nc.pre
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nc.suf = nc.suf + ")"
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return nc, lc, rc
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@ -568,8 +595,28 @@ class _ConvertVisitor(_ConversionMixin):
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self.unaryOp(node, 'not ', context)
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def visitUnaryAdd(self, node, context=None, *args):
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self.unaryOp(node, '+', context)
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def visitUnarySub(self, node, context=None, *args):
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self.unaryOp(node, '-', context)
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n, o = node.vhd, node.vhdOri
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ns, os = n.size, o.size
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nc = _Cast()
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if isinstance(o, vhd_int):
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if isinstance(n, vhd_unsigned):
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nc.pre, nc.suf = "to_unsigned(", ", %s)" % ns
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elif isinstance(n, vhd_signed):
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nc.pre, nc.suf = "to_signed(", ", %s)" % ns
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elif isinstance(n, vhd_int):
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pass
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else:
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self.raiseError(node, "Not implemented")
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## else:
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## self.raiseError(node, "Not implemented")
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self.write(nc.pre)
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self.write("(-")
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self.visit(node.expr, context)
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self.write(")")
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self.write(nc.suf)
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def visitNot(self, node, context=None):
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self.checkOpWithNegIntbv(node.expr, 'not ')
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if isinstance(node.vhd, vhd_std_logic):
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@ -808,21 +855,26 @@ class _ConvertVisitor(_ConversionMixin):
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compiler.walk(node.ast, v)
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def visitCompare(self, node, *args):
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context = None
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if node.signed:
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context = _context.SIGNED
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if isinstance(node.vhd, vhd_std_logic):
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self.write("to_std_logic")
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self.write("(")
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self.visit(node.expr, context)
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n = node.vhd
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ns = node.vhd.size
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pre, suf = "(", ")"
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if isinstance(n, vhd_std_logic):
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pre = "to_std_logic("
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elif isinstance(n, vhd_unsigned):
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pre, suf = "to_unsigned(", ", %s)" % ns
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elif isinstance(n, vhd_signed):
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pre, suf = "to_signed(", ", %s)" % ns
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self.write(pre)
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self.visit(node.expr)
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op, code = node.ops[0]
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if op == "==":
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op = "="
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elif op == "!=":
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op = "/="
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self.write(" %s " % op)
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self.visit(code, context)
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self.write(")")
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self.visit(code)
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self.write(suf)
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def visitConst(self, node, context=None, *args):
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if context == _context.PRINT:
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@ -1032,6 +1084,13 @@ class _ConvertVisitor(_ConversionMixin):
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elif isinstance(node.vhd, vhd_unsigned):
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if vhd.size != node.vhd.size:
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s = "resize(%s, %s)" % (n, node.vhd.size)
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elif isinstance(node.vhd, vhd_signed):
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if vhd.size != node.vhd.size:
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s = "signed(resize(%s, %s))" % (n, node.vhd.size)
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else:
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s = "signed(%s)" % n
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elif isinstance(node.vhd, vhd_boolean):
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s = "(%s /= 0)" % n
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else:
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raise NotImplementedError
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@ -1084,14 +1143,16 @@ class _ConvertVisitor(_ConversionMixin):
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elif isinstance(node.vhd, vhd_unsigned):
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if vhd.size != node.vhd.size:
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s = "resize(%s, %s)" % (n, node.vhd.size)
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elif isinstance(node.vhd, vhd_signed):
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if vhd.size != node.vhd.size:
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s = "signed(resize(%s, %s))" % (n, node.vhd.size)
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else:
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s = "signed(%s)" % n
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elif isinstance(node.vhd, vhd_boolean):
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s = "(%s /= 0)" % n
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else:
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print node
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print node.vhd
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raise NotImplementedError
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elif isinstance(vhd, vhd_std_logic) and isinstance(node.vhd, vhd_boolean):
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s = "(%s = '1')" % n
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elif isinstance(vhd, vhd_int):
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@ -1549,6 +1610,11 @@ class vhd_int(vhd_type):
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def toStr(self, constr=True):
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return "integer"
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class vhd_nat(vhd_int):
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def toStr(self, constr=True):
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return "natural"
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class _loopInt(int):
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pass
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@ -1585,6 +1651,13 @@ def inferVhdlObj(obj):
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vhd = vhd_int()
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return vhd
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def maybeNegative(vhd):
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if isinstance(vhd, vhd_signed):
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return True
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if isinstance(vhd, vhd_int) and not isinstance(vhd, vhd_nat):
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return True
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return False
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class _AnnotateTypesVisitor(_ConversionMixin):
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@ -1606,9 +1679,8 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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node.expr.vhd = vhd_int()
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node.vhdOri = node.vhd
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else:
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l, r = node.node.vhd, node.expr.vhd
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self.inferBinaryOpType(node, l, r, node.op)
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node.vhdOri = node.vhd
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left, right = node.node, node.expr
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self.inferBinaryOpType(node, left, right, node.op)
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node.vhd = node.node.vhd
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def visitCallFunc(self, node):
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@ -1635,16 +1707,19 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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node.vhd = node.ast.vhd = inferVhdlObj(node.ast.returnObj)
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def visitCompare(self, node):
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node.vhd = vhd_boolean()
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node.vhd = node.vhdOri = vhd_boolean()
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self.visitChildNodes(node)
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expr = node.expr
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op, code = node.ops[0]
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o = maxType(expr.vhd, code.vhd)
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if isinstance(o, vhd_std_logic):
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expr.vhd = code.vhd = o
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if isinstance(expr.vhd, vhd_std_logic) or isinstance(node.vhd, vhd_std_logic):
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expr.vhd = code.vhd = vhd_std_logic()
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elif isinstance(expr.vhd, vhd_unsigned) and maybeNegative(code.vhd):
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expr.vhd = vhd_signed(expr.vhd.size + 1)
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elif maybeNegative(expr.vhd) and isinstance(code.vhd, vhd_unsigned):
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code.vhd = vhd_signed(code.vhd.size + 1)
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def visitConst(self, node):
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node.vhd = vhd_int()
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node.vhd = vhd_nat()
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def visitFor(self, node):
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self.visitChildNodes(node)
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@ -1668,17 +1743,17 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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def binaryOp(self, node, op=None):
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self.visit(node.left)
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self.visit(node.right)
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r, l = node.right.vhd, node.left.vhd
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self.inferBinaryOpType(node, l, r, op)
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node.vhdOri = node.vhd
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left, right = node.left, node.right
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self.inferBinaryOpType(node, left, right, op)
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def inferBinaryOpType(self, node, l, r, op=None):
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ls, rs = l.size, r.size
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if isinstance(r, vhd_signed) and isinstance(r, vhd_unsigned):
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rs += 1
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if isinstance(r, vhd_unsigned) and isinstance(r, vhd_signed):
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ls += 1
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def inferBinaryOpType(self, node, left, right, op=None):
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if maybeNegative(left.vhd) and isinstance(right.vhd, vhd_unsigned):
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right.vhd = vhd_signed(right.vhd.size + 1)
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if isinstance(left.vhd, vhd_unsigned) and maybeNegative(right.vhd):
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left.vhd = vhd_signed(left.vhd.size + 1)
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l, r = left.vhd, right.vhd
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ls, rs = l.size, r.size
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if isinstance(r, vhd_vector) and isinstance(l, vhd_vector):
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if op in ('+', '-', '+=', '-='):
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s = max(ls, rs)
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@ -1712,6 +1787,7 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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node.vhd = vhd_unsigned(s)
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else:
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node.vhd = vhd_int()
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node.vhdOri = node.vhd
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def visitAdd(self, node):
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@ -1743,10 +1819,6 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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node.vhd = vhd_boolean()
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visitAnd = visitOr = multiBoolOp
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def visitNot(self, node):
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self.visit(node.expr)
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node.vhd = node.expr.vhd = vhd_boolean()
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def visitIf(self, node):
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self.visitChildNodes(node)
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for test, suite in node.tests:
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@ -1760,6 +1832,10 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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def visitListComp(self, node):
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pass # do nothing
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def visitNot(self, node):
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self.visit(node.expr)
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node.vhd = node.expr.vhd = vhd_boolean()
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def visitSlice(self, node):
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self.visitChildNodes(node)
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@ -1793,7 +1869,16 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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self.visit(node.expr)
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node.vhd = node.expr.vhd
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visitUnaryAdd = visitUnarySub = unaryOp
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visitUnaryAdd = unaryOp
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def visitUnarySub(self, node):
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self.visit(node.expr)
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node.vhd = node.expr.vhd
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if isinstance(node.vhd, vhd_unsigned):
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node.vhd = vhd_signed(node.vhd.size + 1)
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elif isinstance(node.vhd, vhd_nat):
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node.vhd = vhd_int()
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node.vhdOri = node.vhd
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def visitWhile(self, node):
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self.visitChildNodes(node)
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565
myhdl/test/toVHDL/test_signed.py
Normal file
565
myhdl/test/toVHDL/test_signed.py
Normal file
@ -0,0 +1,565 @@
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import os
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path = os.path
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import random
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from random import randrange
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random.seed(2)
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from myhdl import *
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## def binaryOps(
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## ## Bitand,
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## ## Bitor,
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## ## Bitxor,
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## ## FloorDiv,
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## LeftShift,
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## ## Mod,
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## Mul,
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## ## Pow,
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## RightShift,
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## Sub,
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## Sum, Sum1, Sum2, Sum3,
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## EQ,
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## NE,
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## LT,
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## GT,
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## LE,
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## GE,
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## And,
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## Or,
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## left, right, bit):
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## while 1:
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## yield left, right
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## ## Bitand.next = left & right
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## ## Bitor.next = left | right
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## ## Bitxor.next = left ^ right
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## ## if right != 0:
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## ## FloorDiv.next = left // right
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## if left < 256 and right < 40 and right >= 0:
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## LeftShift.next = left << right
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## ## if right != 0:
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## ## Mod.next = left % right
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## Mul.next = left * right
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## ## # Icarus doesn't support ** yet
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## ## #if left < 256 and right < 40:
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## ## # Pow.next = left ** right
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## ## Pow.next = 0
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## if right >= -0:
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## RightShift.next = left >> right
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## ## RightShift.next = left
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## Sub.next = left - right
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## Sum.next = left + right
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## Sum1.next = left + right[2:]
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## Sum2.next = left + right[1]
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## Sum3.next = left + bit
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## EQ.next = left == right
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## NE.next = left != right
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## LT.next = left < right
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## GT.next = left > right
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## LE.next = left <= right
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## GE.next = left >= right
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## And.next = bool(left) and bool(right)
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## Or.next = bool(left) or bool(right)
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## def binaryOps_v(name,
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## ## Bitand,
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## ## Bitor,
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## ## Bitxor,
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## ## FloorDiv,
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## LeftShift,
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## ## Mod,
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## Mul,
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## ## Pow,
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## RightShift,
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## Sub,
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## Sum, Sum1, Sum2, Sum3,
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## EQ,
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## NE,
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## LT,
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## GT,
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## LE,
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## GE,
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## And,
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## Or,
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## left, right, bit):
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## return setupCosimulation(**locals())
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## class TestBinaryOps(TestCase):
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## def binaryBench(self, Ll, Ml, Lr, Mr):
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## bit = Signal(bool(0))
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## left = Signal(intbv(min=Ll, max=Ml))
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## right = Signal(intbv(min=Lr, max=Mr))
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## M = 2**14
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## ## Bitand = Signal(intbv(0, min=-2**17, max=2**17))
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## ## Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
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## ## Bitor = Signal(intbv(0)[max(m, n):])
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## ## Bitor_v = Signal(intbv(0)[max(m, n):])
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## ## Bitxor = Signal(intbv(0)[max(m, n):])
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## ## Bitxor_v = Signal(intbv(0)[max(m, n):])
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## ## FloorDiv = Signal(intbv(0)[m:])
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## ## FloorDiv_v = Signal(intbv(0)[m:])
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## LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
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## LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64))
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## ## Mod = Signal(intbv(0)[m:])
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## ## Mod_v = Signal(intbv(0)[m:])
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## Mul = Signal(intbv(0, min=-2**17, max=2**17))
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## Mul_v = Signal(intbv(0, min=-2**17, max=2**17))
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## ## Pow = Signal(intbv(0)[64:])
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## ## Pow_v = Signal(intbv(0)[64:])
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||||
## RightShift = Signal(intbv(0, min=-M, max=M))
|
||||
## RightShift_v = Signal(intbv(0, min=-M, max=M))
|
||||
## Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
|
||||
## Sub_v, Sub1_v, Sub2_v, Sub3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
|
||||
## Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
|
||||
## Sum_v, Sum1_v, Sum2_v, Sum3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
|
||||
## EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
|
||||
## EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)]
|
||||
## And, Or = [Signal(bool()) for i in range(2)]
|
||||
## And_v, Or_v, = [Signal(bool()) for i in range(2)]
|
||||
|
||||
## binops = toVerilog(binaryOps,
|
||||
## ## Bitand,
|
||||
## ## Bitor,
|
||||
## ## Bitxor,
|
||||
## ## FloorDiv,
|
||||
## LeftShift,
|
||||
## ## Mod,
|
||||
## Mul,
|
||||
## ## Pow,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum, Sum1, Sum2, Sum3,
|
||||
## EQ,
|
||||
## NE,
|
||||
## LT,
|
||||
## GT,
|
||||
## LE,
|
||||
## GE,
|
||||
## And,
|
||||
## Or,
|
||||
## left, right, bit)
|
||||
## binops_v = binaryOps_v(binaryOps.func_name,
|
||||
## ## Bitand_v,
|
||||
## ## Bitor_v,
|
||||
## ## Bitxor_v,
|
||||
## ## FloorDiv_v,
|
||||
## LeftShift_v,
|
||||
## ## Mod_v,
|
||||
## Mul_v,
|
||||
## ## Pow_v,
|
||||
## RightShift_v,
|
||||
## Sub_v,
|
||||
## Sum_v, Sum1_v, Sum2_v, Sum3_v,
|
||||
## EQ_v,
|
||||
## NE_v,
|
||||
## LT_v,
|
||||
## GT_v,
|
||||
## LE_v,
|
||||
## GE_v,
|
||||
## And_v,
|
||||
## Or_v,
|
||||
## left, right, bit)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(100):
|
||||
## bit.next = False
|
||||
## left.next = randrange(Ll, Ml)
|
||||
## right.next = randrange(Lr, Mr)
|
||||
## yield delay(10)
|
||||
## for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
|
||||
## left.next = j
|
||||
## right.next = k
|
||||
## yield delay(10)
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield left, right
|
||||
## bit.next = not bit
|
||||
## yield delay(1)
|
||||
|
||||
## #print "%s %s %s %s" % (left, right, Mul, Mul_v)
|
||||
## #print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
|
||||
## #print "%s %s %s %s" % (left, right, Sum, Sum_v)
|
||||
## #print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
|
||||
## ## print left
|
||||
## ## print right
|
||||
## ## print bin(left)
|
||||
## ## print bin(right)
|
||||
## ## print bin(Bitand)
|
||||
## ## print bin(Bitand_v)
|
||||
## ## print Bitand
|
||||
## ## print Bitand_v
|
||||
## ## self.assertEqual(Bitand, Bitand_v)
|
||||
## #w = len(Bitand)
|
||||
## #self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
|
||||
## ## self.assertEqual(Bitor, Bitor_v)
|
||||
## ## self.assertEqual(Bitxor, Bitxor_v)
|
||||
## ## self.assertEqual(FloorDiv, FloorDiv_v)
|
||||
## self.assertEqual(LeftShift, LeftShift_v)
|
||||
## ## self.assertEqual(Mod, Mod_v)
|
||||
## self.assertEqual(Mul, Mul_v)
|
||||
## # self.assertEqual(Pow, Pow_v)
|
||||
## self.assertEqual(RightShift, RightShift_v)
|
||||
## self.assertEqual(Sub, Sub_v)
|
||||
## self.assertEqual(Sum, Sum_v)
|
||||
## self.assertEqual(Sum1, Sum1_v)
|
||||
## self.assertEqual(Sum2, Sum2_v)
|
||||
## self.assertEqual(Sum3, Sum3_v)
|
||||
## self.assertEqual(EQ, EQ_v)
|
||||
## self.assertEqual(NE, NE_v)
|
||||
## self.assertEqual(LT, LT_v)
|
||||
## self.assertEqual(GT, GT_v)
|
||||
## self.assertEqual(LE, LE_v)
|
||||
## self.assertEqual(GE, GE_v)
|
||||
## self.assertEqual(And, And_v)
|
||||
## self.assertEqual(Or, Or_v)
|
||||
|
||||
## return binops, binops_v, stimulus(), check()
|
||||
|
||||
|
||||
## def testBinaryOps(self):
|
||||
## for Ll, Ml, Lr, Mr in (
|
||||
## (-254, 236, 0, 4),
|
||||
## (-128, 128, -128, 128),
|
||||
## (-53, 25, -23, 123),
|
||||
## (-23, 145, -66, 12),
|
||||
## (23, 34, -34, -16),
|
||||
## (-54, -20, 45, 73),
|
||||
## (-25, -12, -123, -66),
|
||||
## ):
|
||||
## sim = self.binaryBench(Ll, Ml, Lr, Mr)
|
||||
## Simulation(sim).run()
|
||||
|
||||
|
||||
|
||||
## def unaryOps(
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg):
|
||||
## while 1:
|
||||
## yield arg
|
||||
## Not.next = not arg
|
||||
## # Invert.next = ~arg
|
||||
## UnaryAdd.next = +arg
|
||||
## UnarySub.next = --arg
|
||||
|
||||
## def unaryOps_v(name,
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg):
|
||||
## return setupCosimulation(**locals())
|
||||
|
||||
|
||||
|
||||
## class TestUnaryOps(TestCase):
|
||||
|
||||
## def unaryBench(self, m):
|
||||
|
||||
## M = 2**m
|
||||
|
||||
## arg = Signal(intbv(0, min=-M, max=+M))
|
||||
## Not = Signal(bool(0))
|
||||
## Not_v = Signal(bool(0))
|
||||
## Invert = Signal(intbv(0, min=-M, max=+M))
|
||||
## Invert_v = Signal(intbv(0, min=-M, max=+M))
|
||||
## UnaryAdd = Signal(intbv(0, min=-M, max=+M))
|
||||
## UnaryAdd_v = Signal(intbv(0, min=-M, max=+M))
|
||||
## UnarySub = Signal(intbv(0, min=-M, max=+M))
|
||||
## UnarySub_v = Signal(intbv(0, min=-M, max=+M))
|
||||
|
||||
## unaryops = toVerilog(unaryOps,
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg)
|
||||
## unaryops_v = unaryOps_v(unaryOps.func_name,
|
||||
## Not_v,
|
||||
## Invert_v,
|
||||
## UnaryAdd_v,
|
||||
## UnarySub_v,
|
||||
## arg)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(-M, M):
|
||||
## arg.next = intbv(i)
|
||||
## yield delay(10)
|
||||
## for i in range(100):
|
||||
## arg.next = randrange(-M, M)
|
||||
## yield delay(10)
|
||||
## raise StopSimulation
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield arg
|
||||
## yield delay(1)
|
||||
## self.assertEqual(Not, Not_v)
|
||||
## #self.assertEqual(Invert, Invert_v)
|
||||
## self.assertEqual(UnaryAdd, UnaryAdd_v)
|
||||
## self.assertEqual(UnarySub, UnarySub_v)
|
||||
|
||||
## return unaryops, unaryops_v, stimulus(), check()
|
||||
|
||||
## def testUnaryOps(self):
|
||||
## for m in (4, 7):
|
||||
## sim = self.unaryBench(m)
|
||||
## Simulation(sim).run()
|
||||
|
||||
|
||||
## def augmOps(
|
||||
## ## Bitand,
|
||||
## ## Bitor,
|
||||
## ## Bitxor,
|
||||
## ## FloorDiv,
|
||||
## LeftShift,
|
||||
## ## Mod,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right):
|
||||
## var = intbv(0, min=-2**17, max=+2**17)
|
||||
## var2 = intbv(0, min=-2**64, max=+2**64)
|
||||
## while 1:
|
||||
## yield left, right
|
||||
## ## var[:] = left
|
||||
## ## var &= right
|
||||
## ## Bitand.next = var
|
||||
## ## var[:] = left
|
||||
## ## var |= right
|
||||
## ## Bitor.next = var
|
||||
## ## var[:] = left
|
||||
## ## var ^= left
|
||||
## ## Bitxor.next = var
|
||||
## ## if right != 0:
|
||||
## ## var[:] = left
|
||||
## ## var //= right
|
||||
## ## FloorDiv.next = var
|
||||
## if left < 256 and right < 40 and right >= 0:
|
||||
## var2[:] = left
|
||||
## var2 <<= right
|
||||
## LeftShift.next = var2
|
||||
## ## if right != 0:
|
||||
## ## var[:] = left
|
||||
## ## var %= right
|
||||
## ## Mod.next = var
|
||||
## var[:] = left
|
||||
## var *= right
|
||||
## Mul.next = var
|
||||
|
||||
## var[:] = left
|
||||
## if right >= 0:
|
||||
## var >>= right
|
||||
## RightShift.next = var
|
||||
|
||||
## var[:] = left
|
||||
## var -= right
|
||||
## Sub.next = var
|
||||
## var[:] = left
|
||||
## var += right
|
||||
## Sum.next = var
|
||||
|
||||
|
||||
## def augmOps_v( name,
|
||||
## ## Bitand,
|
||||
## ## Bitor,
|
||||
## ## Bitxor,
|
||||
## ## FloorDiv,
|
||||
## LeftShift,
|
||||
## ## Mod,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right):
|
||||
## return setupCosimulation(**locals())
|
||||
|
||||
## class TestAugmOps(TestCase):
|
||||
|
||||
## def augmBench(self, Ll, Ml, Lr, Mr):
|
||||
|
||||
|
||||
## left = Signal(intbv(min=Ll, max=Ml))
|
||||
## right = Signal(intbv(min=Lr, max=Mr))
|
||||
## M = 2**17
|
||||
|
||||
|
||||
## ## Bitand = Signal(intbv(0)[max(m, n):])
|
||||
## ## Bitand_v = Signal(intbv(0)[max(m, n):])
|
||||
## ## Bitor = Signal(intbv(0)[max(m, n):])
|
||||
## ## Bitor_v = Signal(intbv(0)[max(m, n):])
|
||||
## ## Bitxor = Signal(intbv(0)[max(m, n):])
|
||||
## ## Bitxor_v = Signal(intbv(0)[max(m, n):])
|
||||
|
||||
## ## FloorDiv = Signal(intbv(0)[m:])
|
||||
## ## FloorDiv_v = Signal(intbv(0)[m:])
|
||||
## LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
|
||||
## LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64))
|
||||
## ## Mod = Signal(intbv(0)[m:])
|
||||
## ## Mod_v = Signal(intbv(0)[m:])
|
||||
|
||||
## Mul = Signal(intbv(0, min=-M, max=+M))
|
||||
## Mul_v = Signal(intbv(0, min=-M, max=+M))
|
||||
|
||||
## RightShift = Signal(intbv(0, min=-M, max=+M))
|
||||
## RightShift_v = Signal(intbv(0, min=-M, max=+M))
|
||||
|
||||
## Sub = Signal(intbv(0, min=-M, max=+M))
|
||||
## Sub_v = Signal(intbv(0, min=-M, max=+M))
|
||||
## Sum = Signal(intbv(0, min=-M, max=+M))
|
||||
## Sum_v = Signal(intbv(0, min=-M, max=+M))
|
||||
|
||||
## augmops = toVerilog(augmOps,
|
||||
## ## Bitand,
|
||||
## ## Bitor,
|
||||
## ## Bitxor,
|
||||
## ## FloorDiv,
|
||||
## LeftShift,
|
||||
## ## Mod,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right)
|
||||
## augmops_v = augmOps_v( augmOps.func_name,
|
||||
## ## Bitand_v,
|
||||
## ## Bitor_v,
|
||||
## ## Bitxor_v,
|
||||
## ## FloorDiv_v,
|
||||
## LeftShift_v,
|
||||
## ## Mod_v,
|
||||
## Mul_v,
|
||||
## RightShift_v,
|
||||
## Sub_v,
|
||||
## Sum_v,
|
||||
## left, right)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(100):
|
||||
## left.next = randrange(Ll, Ml)
|
||||
## right.next = randrange(Lr, Mr)
|
||||
## yield delay(10)
|
||||
## for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
|
||||
## left.next = j
|
||||
## right.next = k
|
||||
## yield delay(10)
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield left, right
|
||||
## yield delay(1)
|
||||
## # print "%s %s %s %s" % (left, right, Or, Or_v)
|
||||
## ## self.assertEqual(Bitand, Bitand_v)
|
||||
## ## self.assertEqual(Bitor, Bitor_v)
|
||||
## ## self.assertEqual(Bitxor, Bitxor_v)
|
||||
## ## self.assertEqual(FloorDiv, FloorDiv_v)
|
||||
## ## self.assertEqual(LeftShift, LeftShift_v)
|
||||
## ## self.assertEqual(Mod, Mod_v)
|
||||
## self.assertEqual(Mul, Mul_v)
|
||||
## self.assertEqual(RightShift, RightShift_v)
|
||||
## self.assertEqual(Sub, Sub_v)
|
||||
## self.assertEqual(Sum, Sum_v)
|
||||
|
||||
## return augmops, augmops_v, stimulus(), check()
|
||||
|
||||
|
||||
## def testAugmOps(self):
|
||||
## for Ll, Ml, Lr, Mr in (
|
||||
## (-254, 236, 0, 4),
|
||||
## (-128, 128, -128, 128),
|
||||
## (-53, 25, -23, 123),
|
||||
## (-23, 145, -66, 12),
|
||||
## (23, 34, -34, -16),
|
||||
## (-54, -20, 45, 73),
|
||||
## (-25, -12, -123, -66),
|
||||
## ):
|
||||
## sim = self.augmBench(Ll, Ml, Lr, Mr)
|
||||
## Simulation(sim).run()
|
||||
|
||||
|
||||
def expressions(a, b, clk):
|
||||
|
||||
c = Signal(intbv(0, min=0, max=47))
|
||||
e = Signal(bool())
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
|
||||
d = intbv(0, min=-23, max=43)
|
||||
d[:] = -17
|
||||
|
||||
c.next = 5
|
||||
yield clk.posedge
|
||||
a.next = c + 1
|
||||
b.next = c + 1
|
||||
yield clk.posedge
|
||||
a.next = c + -10
|
||||
b.next = c + -1
|
||||
yield clk.posedge
|
||||
a.next = c < -10
|
||||
b.next = c < -1
|
||||
yield clk.posedge
|
||||
a.next = d + c
|
||||
b.next = d >= c
|
||||
yield clk.posedge
|
||||
## a.next = d & c
|
||||
## b.next = c + (d & c)
|
||||
yield clk.posedge
|
||||
a.next = d + -c
|
||||
b.next = c + (-d)
|
||||
yield clk.posedge
|
||||
a.next = -d
|
||||
yield clk.posedge
|
||||
a.next = -c
|
||||
yield clk.posedge
|
||||
|
||||
|
||||
yield clk.posedge
|
||||
raise StopSimulation
|
||||
|
||||
return logic
|
||||
|
||||
|
||||
|
||||
def expressionsBench():
|
||||
|
||||
a = Signal(intbv(0, min=-34, max=47))
|
||||
b = Signal(intbv(0, min=0, max=47))
|
||||
clk = Signal(bool())
|
||||
|
||||
expr = expressions(a, b, clk)
|
||||
|
||||
@instance
|
||||
def check():
|
||||
while 1:
|
||||
yield clk.posedge
|
||||
yield delay(1)
|
||||
print int(a)
|
||||
print int(b)
|
||||
|
||||
@instance
|
||||
def clkgen():
|
||||
while True:
|
||||
yield delay(10)
|
||||
clk.next = not clk
|
||||
|
||||
return expr, check, clkgen
|
||||
|
||||
|
||||
def testExpressions():
|
||||
assert conversion.verify(expressionsBench) == 0
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user