signed expressions

myhdl/conversion/_toVHDL.py

@@ -171,13 +171,38 @@ def _writeModuleHeader(f, intf):
 
 
 funcdecls = """\
-function to_std_logic (arg : boolean) return std_logic is begin
+function to_std_logic (arg: boolean) return std_logic is
+begin
     if arg then
         return '1';
     else
         return '0';
     end if;
 end function to_std_logic;
+
+function to_unsigned (arg: boolean; size: natural) return unsigned is
+    variable res: unsigned(size-1 downto 0) := (others => '0');
+begin
+    if arg then
+        res(0):= '1';
+    end if;
+    return res;
+end function to_unsigned;
+
+function to_signed (arg: boolean; size: natural) return signed is
+    variable res: signed(size-1 downto 0) := (others => '0');
+begin
+    if arg then
+        res(0) := '1';
+    end if;
+    return res; 
+end function to_signed;
+
+function "-" (arg: unsigned) return signed is
+begin
+    return - signed(resize(arg, arg'length+1));
+end function "-";
+
 """
 
 def _writeFuncDecls(f):
@@ -408,7 +433,7 @@ class _ConvertVisitor(_ConversionMixin):
 
     def binaryOp(self, node, op=None):
         n, o, l, r = node.vhd, node.vhdOri, node.left.vhd, node.right.vhd
-        nc, rc, lc = self.inferBinaryOpCasts(node, n, o, l, r, op)
+        nc, lc, rc = self.inferBinaryOpCasts(node, n, o, l, r, op)
         context = None
         self.write(nc.pre)
         self.write("(")
@@ -429,28 +454,30 @@ class _ConvertVisitor(_ConversionMixin):
         nc, lc, rc = [_Cast() for i in range(3)]
         if isinstance(o, vhd_int):
             if isinstance(n, vhd_unsigned):
-                nc.pre, nc.suf = "to_unsigned(", ", %s)" % node.vhd.size
+                nc.pre, nc.suf = "to_unsigned(", ", %s)" % ns
             elif isinstance(n, vhd_signed):
-                nc.pre, nc.suf = "to_signed(", ", %s)" % node.vhd.size
+                nc.pre, nc.suf = "to_signed(", ", %s)" % ns
             elif isinstance(n, vhd_int):
                 pass
             else:
                 self.raiseError(node, "Not implemented")
-        elif isinstance(l, vhd_unsigned) and isinstance(r, (vhd_int, vhd_unsigned)):
+        elif isinstance(l, vhd_vector) and isinstance(r, (vhd_int, vhd_vector)):
-            print "HERE1"
-            print op
             if ds < 0:
                 nc.pre, nc.suf = "resize(", ", %s)" % ns
             elif ds > 0:
-                print "HERE"
-                print op
                 if op in ('+', '-', '/'):
                     lc.pre, lc.suf = "resize(", ", %s)" % ns
                 elif op in ('mod', ):
-                    print 'MOD HERE'
                     nc.pre, nc.suf = "resize(", ", %s)" % ns
                 else:
                     self.raiseError(node, "Not implemented")
+        if isinstance(n, vhd_signed) and isinstance(o, vhd_unsigned):
+            nc.pre = "signed(" + nc.pre
+            nc.suf = nc.suf + ")"
+        elif isinstance(n, vhd_unsigned) and isinstance(o, vhd_signed):
+            nc.pre = "unsigned(" + nc.pre
+            nc.suf = nc.suf + ")"
+        
                 
         return nc, lc, rc
 
@@ -568,8 +595,28 @@ class _ConvertVisitor(_ConversionMixin):
         self.unaryOp(node, 'not ', context)
     def visitUnaryAdd(self, node, context=None, *args):
         self.unaryOp(node, '+', context)
+        
     def visitUnarySub(self, node, context=None, *args):
-        self.unaryOp(node, '-', context)
+        n, o = node.vhd, node.vhdOri
+        ns, os = n.size, o.size
+        nc = _Cast()
+        if isinstance(o, vhd_int):
+            if isinstance(n, vhd_unsigned):
+                nc.pre, nc.suf = "to_unsigned(", ", %s)" % ns
+            elif isinstance(n, vhd_signed):
+                nc.pre, nc.suf = "to_signed(", ", %s)" % ns
+            elif isinstance(n, vhd_int):
+                pass
+            else:
+                self.raiseError(node, "Not implemented")
+##         else:
+##             self.raiseError(node, "Not implemented")
+        self.write(nc.pre)
+        self.write("(-")
+        self.visit(node.expr, context)
+        self.write(")")
+        self.write(nc.suf)
+       
     def visitNot(self, node, context=None):
         self.checkOpWithNegIntbv(node.expr, 'not ')
         if isinstance(node.vhd, vhd_std_logic):
@@ -808,21 +855,26 @@ class _ConvertVisitor(_ConversionMixin):
             compiler.walk(node.ast, v)
 
     def visitCompare(self, node, *args):
-        context = None
+        n = node.vhd
-        if node.signed:
+        ns = node.vhd.size
-            context = _context.SIGNED
+        pre, suf = "(", ")"
-        if isinstance(node.vhd, vhd_std_logic):
+        if isinstance(n, vhd_std_logic):
-            self.write("to_std_logic")
+            pre = "to_std_logic("
-        self.write("(")
+        elif isinstance(n, vhd_unsigned):
-        self.visit(node.expr, context)
+            pre, suf = "to_unsigned(", ", %s)" % ns
+        elif isinstance(n, vhd_signed):
+            pre, suf = "to_signed(", ", %s)" % ns
+            
+        self.write(pre)
+        self.visit(node.expr)
         op, code = node.ops[0]
         if op == "==":
             op = "="
         elif op == "!=":
             op = "/="
         self.write(" %s " % op)
-        self.visit(code, context)
+        self.visit(code)
-        self.write(")")
+        self.write(suf)
 
     def visitConst(self, node, context=None, *args):
         if context == _context.PRINT:
@@ -1032,6 +1084,13 @@ class _ConvertVisitor(_ConversionMixin):
                 elif isinstance(node.vhd, vhd_unsigned):
                     if vhd.size != node.vhd.size:
                         s = "resize(%s, %s)" % (n, node.vhd.size)
+                elif isinstance(node.vhd, vhd_signed):
+                    if vhd.size != node.vhd.size:
+                        s = "signed(resize(%s, %s))" % (n, node.vhd.size)
+                    else:
+                        s = "signed(%s)" % n
+                elif isinstance(node.vhd, vhd_boolean):
+                    s = "(%s /= 0)" % n
                 else:
                     raise NotImplementedError
 
@@ -1084,14 +1143,16 @@ class _ConvertVisitor(_ConversionMixin):
                         elif isinstance(node.vhd, vhd_unsigned):
                             if vhd.size != node.vhd.size:
                                 s = "resize(%s, %s)" % (n, node.vhd.size)
+                        elif isinstance(node.vhd, vhd_signed):
+                            if vhd.size != node.vhd.size:
+                                s = "signed(resize(%s, %s))" % (n, node.vhd.size)
+                            else:
+                                s = "signed(%s)" % n
                         elif isinstance(node.vhd, vhd_boolean):
                             s = "(%s /= 0)" % n
                         else:
-                            print node
-                            print node.vhd
                             raise NotImplementedError
 
-
                     elif isinstance(vhd, vhd_std_logic) and isinstance(node.vhd, vhd_boolean):
                         s = "(%s = '1')" %  n
                     elif isinstance(vhd, vhd_int):
@@ -1549,6 +1610,11 @@ class vhd_int(vhd_type):
     def toStr(self, constr=True):
         return "integer"
 
+class vhd_nat(vhd_int):
+    def toStr(self, constr=True):
+        return "natural"
+    
+
 class _loopInt(int):
     pass
 
@@ -1585,6 +1651,13 @@ def inferVhdlObj(obj):
         vhd = vhd_int()
     return vhd
 
+def maybeNegative(vhd):
+    if isinstance(vhd, vhd_signed):
+        return True
+    if isinstance(vhd, vhd_int) and not isinstance(vhd, vhd_nat):
+        return True
+    return False
+
         
 class _AnnotateTypesVisitor(_ConversionMixin):
 
@@ -1606,9 +1679,8 @@ class _AnnotateTypesVisitor(_ConversionMixin):
             node.expr.vhd = vhd_int()           
             node.vhdOri = node.vhd
         else:
-             l, r = node.node.vhd, node.expr.vhd
+             left, right = node.node, node.expr
-             self.inferBinaryOpType(node, l, r, node.op)
+             self.inferBinaryOpType(node, left, right, node.op)
-             node.vhdOri = node.vhd
         node.vhd = node.node.vhd
         
     def visitCallFunc(self, node):
@@ -1635,16 +1707,19 @@ class _AnnotateTypesVisitor(_ConversionMixin):
             node.vhd = node.ast.vhd = inferVhdlObj(node.ast.returnObj)
     
     def visitCompare(self, node):
-        node.vhd = vhd_boolean()
+        node.vhd = node.vhdOri = vhd_boolean()
         self.visitChildNodes(node)
         expr = node.expr
         op, code = node.ops[0]
-        o = maxType(expr.vhd, code.vhd)
+        if isinstance(expr.vhd, vhd_std_logic) or isinstance(node.vhd, vhd_std_logic):
-        if isinstance(o, vhd_std_logic):
+            expr.vhd = code.vhd = vhd_std_logic()
-            expr.vhd = code.vhd = o
+        elif isinstance(expr.vhd, vhd_unsigned) and maybeNegative(code.vhd):
+            expr.vhd = vhd_signed(expr.vhd.size + 1)
+        elif maybeNegative(expr.vhd) and isinstance(code.vhd, vhd_unsigned):
+            code.vhd = vhd_signed(code.vhd.size + 1)
 
     def visitConst(self, node):
-        node.vhd = vhd_int()
+        node.vhd = vhd_nat()
 
     def visitFor(self, node):
         self.visitChildNodes(node)
@@ -1668,17 +1743,17 @@ class _AnnotateTypesVisitor(_ConversionMixin):
     def binaryOp(self, node, op=None):
         self.visit(node.left)
         self.visit(node.right)
-        r, l = node.right.vhd, node.left.vhd
+        left, right = node.left, node.right
-        self.inferBinaryOpType(node, l, r, op)
+        self.inferBinaryOpType(node, left, right, op)
-        node.vhdOri = node.vhd
 
 
-    def inferBinaryOpType(self, node, l, r, op=None):
+    def inferBinaryOpType(self, node, left, right, op=None):
-        ls, rs = l.size, r.size
+        if maybeNegative(left.vhd) and isinstance(right.vhd, vhd_unsigned):
-        if isinstance(r, vhd_signed) and isinstance(r, vhd_unsigned):
+            right.vhd = vhd_signed(right.vhd.size + 1)
-            rs += 1
+        if isinstance(left.vhd, vhd_unsigned) and maybeNegative(right.vhd):
-        if isinstance(r, vhd_unsigned) and isinstance(r, vhd_signed):
+            left.vhd = vhd_signed(left.vhd.size + 1)
-            ls += 1
+        l, r = left.vhd, right.vhd
+        ls, rs = l.size, r.size       
         if isinstance(r, vhd_vector) and isinstance(l, vhd_vector):
             if op in ('+', '-', '+=', '-='):
                 s = max(ls, rs)
@@ -1712,6 +1787,7 @@ class _AnnotateTypesVisitor(_ConversionMixin):
             node.vhd = vhd_unsigned(s)
         else:
             node.vhd = vhd_int()
+        node.vhdOri = node.vhd
         
 
     def visitAdd(self, node):
@@ -1743,10 +1819,6 @@ class _AnnotateTypesVisitor(_ConversionMixin):
         node.vhd = vhd_boolean()
     visitAnd = visitOr = multiBoolOp
 
-    def visitNot(self, node):
-        self.visit(node.expr)
-        node.vhd = node.expr.vhd = vhd_boolean()
-
     def visitIf(self, node):
         self.visitChildNodes(node)
         for test, suite in node.tests:
@@ -1760,6 +1832,10 @@ class _AnnotateTypesVisitor(_ConversionMixin):
 
     def visitListComp(self, node):
         pass # do nothing
+    
+    def visitNot(self, node):
+        self.visit(node.expr)
+        node.vhd = node.expr.vhd = vhd_boolean()
 
     def visitSlice(self, node):
         self.visitChildNodes(node)
@@ -1793,7 +1869,16 @@ class _AnnotateTypesVisitor(_ConversionMixin):
         self.visit(node.expr)
         node.vhd = node.expr.vhd
 
-    visitUnaryAdd = visitUnarySub = unaryOp
+    visitUnaryAdd = unaryOp
+    
+    def visitUnarySub(self, node):
+        self.visit(node.expr)
+        node.vhd = node.expr.vhd
+        if isinstance(node.vhd, vhd_unsigned):
+            node.vhd = vhd_signed(node.vhd.size + 1)
+        elif isinstance(node.vhd, vhd_nat):
+            node.vhd = vhd_int()
+        node.vhdOri = node.vhd
 
     def visitWhile(self, node):
         self.visitChildNodes(node)

myhdl/test/toVHDL/test_signed.py

@@ -0,0 +1,565 @@
+import os
+path = os.path
+import random
+from random import randrange
+random.seed(2)
+
+from myhdl import *
+
+
+
+
+## def binaryOps(
+## ##                 Bitand,
+## ##               Bitor,
+## ##               Bitxor,
+## ##               FloorDiv,
+##               LeftShift,
+## ##               Mod,
+##                  Mul,
+## ##               Pow,
+##                  RightShift,
+##                  Sub,
+##                  Sum, Sum1, Sum2, Sum3,
+##                  EQ,
+##                  NE,
+##                  LT,
+##                  GT,
+##                  LE,
+##                  GE,
+##                  And,
+##                  Or,
+##                  left, right, bit):
+
+##     while 1:
+##         yield left, right
+## ##        Bitand.next = left & right
+## ##         Bitor.next = left | right
+## ##         Bitxor.next = left ^ right
+## ##         if right != 0:
+## ##             FloorDiv.next = left // right
+##         if left < 256 and right < 40  and right >= 0:
+##             LeftShift.next = left << right
+## ##         if right != 0:
+## ##             Mod.next = left % right
+##         Mul.next = left * right
+## ##         # Icarus doesn't support ** yet
+## ##         #if left < 256 and right < 40:
+## ##         #    Pow.next = left ** right
+## ##         Pow.next = 0
+##         if right >= -0:
+##            RightShift.next = left >> right
+##             ## RightShift.next = left
+##         Sub.next = left - right
+##         Sum.next = left + right
+##         Sum1.next = left + right[2:]
+##         Sum2.next = left + right[1]
+##         Sum3.next = left + bit
+##         EQ.next = left == right
+##         NE.next = left != right
+##         LT.next = left < right
+##         GT.next = left > right
+##         LE.next = left <= right
+##         GE.next = left >= right
+##         And.next = bool(left) and bool(right)
+##         Or.next = bool(left) or bool(right)
+
+
+
+## def binaryOps_v(name,
+## ##                Bitand,
+## ##                 Bitor,
+## ##                 Bitxor,
+## ##                 FloorDiv,
+##                 LeftShift,
+## ##                 Mod,
+##                 Mul,
+## ##                 Pow,
+##                 RightShift,
+##                 Sub,
+##                 Sum, Sum1, Sum2, Sum3,
+##                 EQ,
+##                 NE,
+##                 LT,
+##                 GT,
+##                 LE,
+##                 GE,
+##                 And,
+##                 Or,
+##                 left, right, bit):
+##     return setupCosimulation(**locals())
+
+## class TestBinaryOps(TestCase):
+
+##     def binaryBench(self, Ll, Ml, Lr, Mr):
+
+##         bit = Signal(bool(0))
+##         left = Signal(intbv(min=Ll, max=Ml))
+##         right = Signal(intbv(min=Lr, max=Mr))
+##         M = 2**14
+## ##        Bitand = Signal(intbv(0, min=-2**17, max=2**17))
+## ##        Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
+## ##         Bitor = Signal(intbv(0)[max(m, n):])
+## ##         Bitor_v = Signal(intbv(0)[max(m, n):])
+## ##         Bitxor = Signal(intbv(0)[max(m, n):])
+## ##         Bitxor_v = Signal(intbv(0)[max(m, n):])
+## ##         FloorDiv = Signal(intbv(0)[m:])
+## ##         FloorDiv_v = Signal(intbv(0)[m:])
+##         LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
+##         LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64))
+## ##         Mod = Signal(intbv(0)[m:])
+## ##         Mod_v = Signal(intbv(0)[m:])
+##         Mul = Signal(intbv(0, min=-2**17, max=2**17))
+##         Mul_v = Signal(intbv(0, min=-2**17, max=2**17))
+## ##         Pow = Signal(intbv(0)[64:])
+## ##         Pow_v = Signal(intbv(0)[64:])
+##         RightShift = Signal(intbv(0, min=-M, max=M))
+##         RightShift_v = Signal(intbv(0, min=-M, max=M))
+##         Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
+##         Sub_v, Sub1_v, Sub2_v, Sub3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
+##         Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
+##         Sum_v, Sum1_v, Sum2_v, Sum3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
+##         EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
+##         EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)]
+##         And, Or = [Signal(bool()) for i in range(2)]
+##         And_v, Or_v, = [Signal(bool()) for i in range(2)]
+
+##         binops = toVerilog(binaryOps,
+## ##                            Bitand,
+## ##                            Bitor,
+## ##                            Bitxor,
+## ##                            FloorDiv,
+##                            LeftShift,
+## ##                            Mod,
+##                            Mul,
+## ##                            Pow,
+##                            RightShift,
+##                            Sub,
+##                            Sum, Sum1, Sum2, Sum3,
+##                            EQ,
+##                            NE,
+##                            LT,
+##                            GT,
+##                            LE,
+##                            GE,
+##                            And,
+##                            Or,
+##                            left, right, bit)
+##         binops_v = binaryOps_v(binaryOps.func_name,
+## ##                                Bitand_v,
+## ##                                Bitor_v,
+## ##                                Bitxor_v,
+## ##                                FloorDiv_v,
+##                                LeftShift_v,
+## ##                                Mod_v,
+##                                Mul_v,
+## ##                                Pow_v,
+##                                RightShift_v,
+##                                Sub_v,
+##                                Sum_v, Sum1_v, Sum2_v, Sum3_v,
+##                                EQ_v,
+##                                NE_v,
+##                                LT_v,
+##                                GT_v,
+##                                LE_v,
+##                                GE_v,
+##                                And_v,
+##                                Or_v,
+##                                left, right, bit)
+
+##         def stimulus():
+##             for i in range(100):
+##                 bit.next = False
+##                 left.next = randrange(Ll, Ml)
+##                 right.next = randrange(Lr, Mr)
+##                 yield delay(10)
+##             for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
+##                 left.next = j
+##                 right.next = k
+##                 yield delay(10)
+
+##         def check():
+##             while 1:
+##                 yield left, right
+##                 bit.next = not bit
+##                 yield delay(1)
+            
+##                 #print "%s %s %s %s" % (left, right, Mul, Mul_v)
+##                 #print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
+##                 #print "%s %s %s %s" % (left, right, Sum, Sum_v)
+##                 #print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
+## ##                 print left
+## ##                 print right
+## ##                 print bin(left)
+## ##                 print bin(right)
+## ##                 print bin(Bitand)
+## ##                 print bin(Bitand_v)
+## ##                 print Bitand
+## ##                 print Bitand_v
+## ##                self.assertEqual(Bitand, Bitand_v)
+##                 #w = len(Bitand)
+##                 #self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
+## ##                 self.assertEqual(Bitor, Bitor_v)
+## ##                 self.assertEqual(Bitxor, Bitxor_v)
+## ##                 self.assertEqual(FloorDiv, FloorDiv_v)
+##                 self.assertEqual(LeftShift, LeftShift_v)
+## ##                 self.assertEqual(Mod, Mod_v)
+##                 self.assertEqual(Mul, Mul_v)
+##                 # self.assertEqual(Pow, Pow_v)
+##                 self.assertEqual(RightShift, RightShift_v)
+##                 self.assertEqual(Sub, Sub_v)
+##                 self.assertEqual(Sum, Sum_v)
+##                 self.assertEqual(Sum1, Sum1_v)
+##                 self.assertEqual(Sum2, Sum2_v)
+##                 self.assertEqual(Sum3, Sum3_v)
+##                 self.assertEqual(EQ, EQ_v)
+##                 self.assertEqual(NE, NE_v)
+##                 self.assertEqual(LT, LT_v)
+##                 self.assertEqual(GT, GT_v)
+##                 self.assertEqual(LE, LE_v)
+##                 self.assertEqual(GE, GE_v)
+##                 self.assertEqual(And, And_v)
+##                 self.assertEqual(Or, Or_v)
+
+##         return binops, binops_v, stimulus(), check()
+    
+
+##     def testBinaryOps(self):
+##         for Ll, Ml, Lr, Mr in (
+##                                 (-254, 236, 0, 4),
+##                                 (-128, 128, -128, 128),
+##                                 (-53, 25, -23, 123),
+##                                 (-23, 145, -66, 12),
+##                                 (23, 34, -34, -16),
+##                                 (-54, -20, 45, 73),
+##                                 (-25, -12, -123, -66),
+##                               ):
+##             sim = self.binaryBench(Ll, Ml, Lr, Mr)
+##             Simulation(sim).run()
+
+
+            
+## def unaryOps(
+##              Not,
+##              Invert,
+##              UnaryAdd,
+##              UnarySub,
+##              arg):
+##     while 1:
+##         yield arg
+##         Not.next = not arg
+##         # Invert.next = ~arg
+##         UnaryAdd.next = +arg
+##         UnarySub.next = --arg
+
+## def unaryOps_v(name,
+##                Not,
+##                Invert,
+##                UnaryAdd,
+##                UnarySub,
+##                arg):
+##    return setupCosimulation(**locals())
+
+
+            
+## class TestUnaryOps(TestCase):
+
+##     def unaryBench(self, m):
+
+##         M = 2**m
+
+##         arg = Signal(intbv(0, min=-M, max=+M))
+##         Not = Signal(bool(0))
+##         Not_v = Signal(bool(0))
+##         Invert = Signal(intbv(0, min=-M, max=+M))
+##         Invert_v = Signal(intbv(0, min=-M, max=+M))
+##         UnaryAdd = Signal(intbv(0, min=-M, max=+M))
+##         UnaryAdd_v = Signal(intbv(0, min=-M, max=+M))
+##         UnarySub = Signal(intbv(0, min=-M, max=+M))
+##         UnarySub_v = Signal(intbv(0, min=-M, max=+M))
+
+##         unaryops = toVerilog(unaryOps,
+##                              Not,
+##                              Invert,
+##                              UnaryAdd,
+##                              UnarySub,
+##                              arg)
+##         unaryops_v = unaryOps_v(unaryOps.func_name,
+##                                 Not_v,
+##                                 Invert_v,
+##                                 UnaryAdd_v,
+##                                 UnarySub_v,
+##                                 arg)
+
+##         def stimulus():
+##             for i in range(-M, M):
+##                 arg.next = intbv(i)
+##                 yield delay(10)
+##             for i in range(100):
+##                 arg.next = randrange(-M, M)
+##                 yield delay(10)
+##             raise StopSimulation
+
+##         def check():
+##             while 1:
+##                 yield arg
+##                 yield delay(1)
+##                 self.assertEqual(Not, Not_v)
+##                 #self.assertEqual(Invert, Invert_v)
+##                 self.assertEqual(UnaryAdd, UnaryAdd_v)
+##                 self.assertEqual(UnarySub, UnarySub_v)
+
+##         return unaryops, unaryops_v, stimulus(), check()
+
+##     def testUnaryOps(self):
+##         for m in (4, 7):
+##             sim = self.unaryBench(m)
+##             Simulation(sim).run()
+
+
+## def augmOps(
+## ##               Bitand,
+## ##               Bitor,
+## ##               Bitxor,
+## ##               FloorDiv,
+##               LeftShift,
+## ##               Mod,
+##               Mul,
+##               RightShift,
+##               Sub,
+##               Sum,
+##               left, right):
+##     var = intbv(0, min=-2**17, max=+2**17)
+##     var2 = intbv(0, min=-2**64, max=+2**64)
+##     while 1:
+##         yield left, right
+## ##         var[:] = left
+## ##         var &= right
+## ##         Bitand.next = var
+## ##         var[:] = left
+## ##         var |= right
+## ##         Bitor.next = var
+## ##         var[:] = left
+## ##         var ^= left
+## ##         Bitxor.next = var
+## ##         if right != 0:
+## ##             var[:] = left
+## ##             var //= right
+## ##             FloorDiv.next = var
+##         if left < 256 and right < 40 and right >= 0:
+##             var2[:] = left
+##             var2 <<= right
+##             LeftShift.next = var2
+## ##         if right != 0:
+## ##             var[:] = left
+## ##             var %= right
+## ##             Mod.next = var
+##         var[:] = left
+##         var *= right
+##         Mul.next = var
+        
+##         var[:] = left
+##         if right >= 0:
+##             var >>= right
+##             RightShift.next = var
+        
+##         var[:] = left
+##         var -= right
+##         Sub.next = var
+##         var[:] = left
+##         var += right
+##         Sum.next = var
+
+
+## def augmOps_v(  name,
+## ##                 Bitand,
+## ##                 Bitor,
+## ##                 Bitxor,
+## ##                 FloorDiv,
+##                 LeftShift,
+## ##                 Mod,
+##                 Mul,
+##                 RightShift,
+##                 Sub,
+##                 Sum,
+##                 left, right):
+##     return setupCosimulation(**locals())
+
+## class TestAugmOps(TestCase):
+
+##     def augmBench(self, Ll, Ml, Lr, Mr):
+
+        
+##         left = Signal(intbv(min=Ll, max=Ml))
+##         right = Signal(intbv(min=Lr, max=Mr))
+##         M = 2**17
+
+        
+## ##         Bitand = Signal(intbv(0)[max(m, n):])
+## ##         Bitand_v = Signal(intbv(0)[max(m, n):])
+## ##         Bitor = Signal(intbv(0)[max(m, n):])
+## ##         Bitor_v = Signal(intbv(0)[max(m, n):])
+## ##         Bitxor = Signal(intbv(0)[max(m, n):])
+## ##         Bitxor_v = Signal(intbv(0)[max(m, n):])
+        
+## ##         FloorDiv = Signal(intbv(0)[m:])
+## ##         FloorDiv_v = Signal(intbv(0)[m:])
+##         LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
+##         LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64))
+## ##         Mod = Signal(intbv(0)[m:])
+## ##         Mod_v = Signal(intbv(0)[m:])
+        
+##         Mul = Signal(intbv(0, min=-M, max=+M))
+##         Mul_v = Signal(intbv(0, min=-M, max=+M))
+        
+##         RightShift = Signal(intbv(0, min=-M, max=+M))
+##         RightShift_v = Signal(intbv(0, min=-M, max=+M))
+
+##         Sub = Signal(intbv(0, min=-M, max=+M))
+##         Sub_v = Signal(intbv(0, min=-M, max=+M))
+##         Sum = Signal(intbv(0, min=-M, max=+M))
+##         Sum_v = Signal(intbv(0, min=-M, max=+M))
+
+##         augmops = toVerilog(augmOps,
+## ##                            Bitand,
+## ##                            Bitor,
+## ##                            Bitxor,
+## ##                            FloorDiv,
+##                            LeftShift,
+## ##                            Mod,
+##                            Mul,
+##                            RightShift,
+##                            Sub,
+##                            Sum,
+##                            left, right)
+##         augmops_v = augmOps_v( augmOps.func_name,
+## ##                                Bitand_v,
+## ##                                Bitor_v,
+## ##                                Bitxor_v,
+## ##                                FloorDiv_v,
+##                                LeftShift_v,
+## ##                                Mod_v,
+##                                Mul_v,
+##                                RightShift_v,
+##                                Sub_v,
+##                                Sum_v,
+##                                left, right)
+
+##         def stimulus():
+##             for i in range(100):
+##                 left.next = randrange(Ll, Ml)
+##                 right.next = randrange(Lr, Mr)
+##                 yield delay(10)
+##             for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
+##                 left.next = j
+##                 right.next = k
+##                 yield delay(10)
+
+##         def check():
+##             while 1:
+##                 yield left, right
+##                 yield delay(1)
+##                 # print "%s %s %s %s" % (left, right, Or, Or_v)
+## ##                 self.assertEqual(Bitand, Bitand_v)
+## ##                 self.assertEqual(Bitor, Bitor_v)
+## ##                 self.assertEqual(Bitxor, Bitxor_v)
+## ##                 self.assertEqual(FloorDiv, FloorDiv_v)
+## ##                 self.assertEqual(LeftShift, LeftShift_v)
+## ##                 self.assertEqual(Mod, Mod_v)
+##                 self.assertEqual(Mul, Mul_v)
+##                 self.assertEqual(RightShift, RightShift_v)
+##                 self.assertEqual(Sub, Sub_v)
+##                 self.assertEqual(Sum, Sum_v)
+
+##         return augmops, augmops_v, stimulus(), check()
+    
+
+##     def testAugmOps(self):
+##        for Ll, Ml, Lr, Mr in (
+##                                 (-254, 236, 0, 4),
+##                                 (-128, 128, -128, 128),
+##                                 (-53, 25, -23, 123),
+##                                 (-23, 145, -66, 12),
+##                                 (23, 34, -34, -16),
+##                                 (-54, -20, 45, 73),
+##                                 (-25, -12, -123, -66),
+##                               ):
+##             sim = self.augmBench(Ll, Ml, Lr, Mr)
+##             Simulation(sim).run()
+
+
+def expressions(a, b, clk):
+
+    c = Signal(intbv(0, min=0, max=47))
+    e = Signal(bool())
+
+    @instance
+    def logic():
+
+        d = intbv(0, min=-23, max=43)
+        d[:] = -17
+
+        c.next = 5
+        yield clk.posedge
+        a.next = c + 1
+        b.next = c + 1
+        yield clk.posedge
+        a.next = c + -10
+        b.next = c + -1
+        yield clk.posedge
+        a.next = c < -10
+        b.next = c < -1
+        yield clk.posedge
+        a.next = d + c
+        b.next = d >= c
+        yield clk.posedge
+##         a.next = d & c
+##         b.next = c + (d & c)
+        yield clk.posedge
+        a.next = d + -c
+        b.next = c + (-d)
+        yield clk.posedge
+        a.next = -d
+        yield clk.posedge
+        a.next = -c
+        yield clk.posedge
+
+
+        yield clk.posedge
+        raise StopSimulation
+
+    return logic
+        
+
+
+def expressionsBench():
+
+    a = Signal(intbv(0, min=-34, max=47))
+    b = Signal(intbv(0, min=0, max=47))
+    clk = Signal(bool())
+
+    expr = expressions(a, b, clk)
+
+    @instance
+    def check():
+        while 1:
+            yield clk.posedge
+            yield delay(1)
+            print int(a)
+            print int(b)
+
+    @instance
+    def clkgen():
+        while True:
+            yield delay(10)
+            clk.next = not clk
+
+    return expr, check, clkgen
+
+
+def testExpressions():
+    assert conversion.verify(expressionsBench) == 0
+
+
+
+