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corrected .vcd representation for array of enums (#426)
corrected pck_myhdl_xx version number, removing the subminor index
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@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
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toVerilog -- function that converts a design to Verilog
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"""
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__version__ = "0.11.43"
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__version__ = "0.11.44"
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class StopSimulation(Exception):
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@ -111,7 +111,7 @@ class _TraceSignalsClass(object):
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h = _getHierarchy(name, dut)
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else:
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warnings.warn(
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"\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html",
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"\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html",
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category=DeprecationWarning,
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stacklevel=2,
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)
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@ -125,7 +125,7 @@ class _TraceSignalsClass(object):
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vcdpath = os.path.join(directory, filename + ".vcd")
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if path.exists(vcdpath):
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if self.tracebackup :
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if self.tracebackup:
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backup = vcdpath[:-4] + '.' + str(path.getmtime(vcdpath)) + '.vcd'
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shutil.copyfile(vcdpath, backup)
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os.remove(vcdpath)
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@ -245,13 +245,15 @@ def _writeVcdSigs(f, hierarchy, tracelists):
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siglist.append(s)
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w = s._nrbits
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# use real for enum strings
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# 03-02-2024-04-2014 jb
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# Impulse has a 'string'type (since 2014, see above
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if w and not isinstance(sval, EnumItemType):
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if w == 1:
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print("$var reg 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
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else:
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print("$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex), file=f)
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else:
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print("$var real 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
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print("$var string 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
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memindex += 1
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print("$upscope $end", file=f)
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for i in range(curlevel):
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@ -64,8 +64,9 @@ from myhdl.conversion._VHDLNameValidation import _nameValid, _usedNames
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from myhdl import bin as tobin
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_version = myhdl.__version__.replace('.', '')
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_shortversion = _version.replace('dev', '')[:-2] # loose the subminor version number
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_shortversion, __, __ = myhdl.__version__.replace('dev', '').rpartition('.') # loose the subminor version number
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_shortversion = _shortversion.replace('.', '')
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_converting = 0
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_profileFunc = None
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_enumPortTypeSet = set()
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@ -223,6 +224,7 @@ class _ToVHDLConvertor(object):
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raise ToVHDLError(_error.PortInList, portname)
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# add enum types to port-related set
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if isinstance(s._val, EnumItemType):
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print('EnumItemType', s._val)
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obj = s._val._type
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if obj in _enumTypeSet:
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_enumTypeSet.remove(obj)
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