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corrected .vcd representation for array of enums (#426)

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corrected  pck_myhdl_xx version number, removing the subminor index
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Josy Boelen 2024-02-03 13:47:47 +01:00 committed by GitHub
parent 7cef85c1c6
commit a0bebbf72d
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3 changed files with 10 additions and 6 deletions
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2
myhdl/__init__.py
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@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
toVerilog -- function that converts a design to Verilog toVerilog -- function that converts a design to Verilog
""" """
__version__ = "0.11.43" __version__ = "0.11.44"
class StopSimulation(Exception): class StopSimulation(Exception):

8
myhdl/_traceSignals.py
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@ -111,7 +111,7 @@ class _TraceSignalsClass(object):
h = _getHierarchy(name, dut) h = _getHierarchy(name, dut)
else: else:
warnings.warn( warnings.warn(
"\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", "\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html",
category=DeprecationWarning, category=DeprecationWarning,
stacklevel=2, stacklevel=2,
) )
@ -125,7 +125,7 @@ class _TraceSignalsClass(object):
vcdpath = os.path.join(directory, filename + ".vcd") vcdpath = os.path.join(directory, filename + ".vcd")
if path.exists(vcdpath): if path.exists(vcdpath):
if self.tracebackup : if self.tracebackup:
backup = vcdpath[:-4] + '.' + str(path.getmtime(vcdpath)) + '.vcd' backup = vcdpath[:-4] + '.' + str(path.getmtime(vcdpath)) + '.vcd'
shutil.copyfile(vcdpath, backup) shutil.copyfile(vcdpath, backup)
os.remove(vcdpath) os.remove(vcdpath)
@ -245,13 +245,15 @@ def _writeVcdSigs(f, hierarchy, tracelists):
siglist.append(s) siglist.append(s)
w = s._nrbits w = s._nrbits
# use real for enum strings # use real for enum strings
# 03-02-2024-04-2014 jb
# Impulse has a 'string'type (since 2014, see above
if w and not isinstance(sval, EnumItemType): if w and not isinstance(sval, EnumItemType):
if w == 1: if w == 1:
print("$var reg 1 %s %s(%i) $end" % (s._code, n, memindex), file=f) print("$var reg 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
else: else:
print("$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex), file=f) print("$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex), file=f)
else: else:
print("$var real 1 %s %s(%i) $end" % (s._code, n, memindex), file=f) print("$var string 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
memindex += 1 memindex += 1
print("$upscope $end", file=f) print("$upscope $end", file=f)
for i in range(curlevel): for i in range(curlevel):

6
myhdl/conversion/_toVHDL.py
View File

@ -64,8 +64,9 @@ from myhdl.conversion._VHDLNameValidation import _nameValid, _usedNames
from myhdl import bin as tobin from myhdl import bin as tobin
_version = myhdl.__version__.replace('.', '') _shortversion, __, __ = myhdl.__version__.replace('dev', '').rpartition('.') # loose the subminor version number
_shortversion = _version.replace('dev', '')[:-2] # loose the subminor version number _shortversion = _shortversion.replace('.', '')
_converting = 0 _converting = 0
_profileFunc = None _profileFunc = None
_enumPortTypeSet = set() _enumPortTypeSet = set()
@ -223,6 +224,7 @@ class _ToVHDLConvertor(object):
raise ToVHDLError(_error.PortInList, portname) raise ToVHDLError(_error.PortInList, portname)
# add enum types to port-related set # add enum types to port-related set
if isinstance(s._val, EnumItemType): if isinstance(s._val, EnumItemType):
print('EnumItemType', s._val)
obj = s._val._type obj = s._val._type
if obj in _enumTypeSet: if obj in _enumTypeSet:
_enumTypeSet.remove(obj) _enumTypeSet.remove(obj)