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jand 2004-02-04 10:53:30 +00:00
parent d0f1e04eff
commit a267226857
1 changed files with 1 additions and 1 deletions
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myhdl/test/toVerilog/Makefile
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@ -2,4 +2,4 @@ all:
python test_all.py
clean:
- rm *.o *.out *.v *.pyc *~
- rm *.o *.out *.v *.pyc *~ *.vcd*