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Factor visitor traversal out to top class
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@ -32,8 +32,6 @@ from myhdl._util import _isGenFunc, _dedent
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from myhdl._Waiter import _Waiter, _SignalWaiter, _SignalTupleWaiter
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from myhdl._Waiter import _Waiter, _SignalWaiter, _SignalTupleWaiter
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from myhdl._instance import _Instantiator
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from myhdl._instance import _Instantiator
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from myhdl._always import _Always
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from myhdl._always import _Always
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from myhdl._resolverefs import _AttrRefTransformer
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from myhdl._visitors import _SigNameVisitor
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class _error:
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class _error:
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pass
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pass
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@ -91,20 +89,11 @@ class _AlwaysComb(_Always):
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senslist = []
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senslist = []
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super(_AlwaysComb, self).__init__(func, senslist)
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super(_AlwaysComb, self).__init__(func, senslist)
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tree = self.ast
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inouts = self.inouts | self.inputs.intersection(self.outputs)
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# print ast.dump(tree)
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v = _AttrRefTransformer(self)
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v.visit(tree)
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v = _SigNameVisitor(self.symdict)
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v.visit(tree)
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self.inputs = v.inputs
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self.outputs = v.outputs
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inouts = v.inouts | self.inputs.intersection(self.outputs)
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if inouts:
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if inouts:
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raise AlwaysCombError(_error.SignalAsInout % inouts)
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raise AlwaysCombError(_error.SignalAsInout % inouts)
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if v.embedded_func:
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if self.embedded_func:
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raise AlwaysCombError(_error.EmbeddedFunction)
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raise AlwaysCombError(_error.EmbeddedFunction)
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for n in self.inputs:
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for n in self.inputs:
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@ -32,8 +32,6 @@ from myhdl._delay import delay
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from myhdl._Signal import _Signal, _WaiterList,_isListOfSigs
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from myhdl._Signal import _Signal, _WaiterList,_isListOfSigs
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from myhdl._Waiter import _Waiter, _EdgeWaiter, _EdgeTupleWaiter
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from myhdl._Waiter import _Waiter, _EdgeWaiter, _EdgeTupleWaiter
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from myhdl._always import _Always
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from myhdl._always import _Always
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from myhdl._resolverefs import _AttrRefTransformer
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from myhdl._visitors import _SigNameVisitor
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# evacuate this later
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# evacuate this later
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AlwaysSeqError = AlwaysError
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AlwaysSeqError = AlwaysError
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@ -101,23 +99,15 @@ class _AlwaysSeq(_Always):
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super(_AlwaysSeq, self).__init__(func, senslist)
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super(_AlwaysSeq, self).__init__(func, senslist)
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# now infer outputs to be reset
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if self.inouts:
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tree = self.ast
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# print ast.dump(tree)
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v = _AttrRefTransformer(self)
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v.visit(tree)
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v = _SigNameVisitor(self.symdict)
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v.visit(tree)
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if v.inouts:
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raise AlwaysSeqError(_error.SigAugAssign, v.inouts)
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raise AlwaysSeqError(_error.SigAugAssign, v.inouts)
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if v.embedded_func:
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if self.embedded_func:
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raise AlwaysSeqError(_error.EmbeddedFunction)
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raise AlwaysSeqError(_error.EmbeddedFunction)
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sigregs = self.sigregs = []
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sigregs = self.sigregs = []
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varregs = self.varregs = []
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varregs = self.varregs = []
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for n in v.outputs:
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for n in self.outputs:
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reg = self.symdict[n]
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reg = self.symdict[n]
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if isinstance(reg, _Signal):
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if isinstance(reg, _Signal):
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sigregs.append(reg)
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sigregs.append(reg)
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@ -26,6 +26,8 @@ from types import FunctionType
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from myhdl import InstanceError
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from myhdl import InstanceError
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from myhdl._util import _isGenFunc, _makeAST
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from myhdl._util import _isGenFunc, _makeAST
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from myhdl._Waiter import _inferWaiter
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from myhdl._Waiter import _inferWaiter
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from myhdl._resolverefs import _AttrRefTransformer
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from myhdl._visitors import _SigNameVisitor
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class _error:
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class _error:
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pass
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pass
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@ -61,6 +63,17 @@ class _Instantiator(object):
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symdict.update(zip(freevars, closure))
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symdict.update(zip(freevars, closure))
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self.symdict = symdict
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self.symdict = symdict
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tree = self.ast
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# print ast.dump(tree)
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v = _AttrRefTransformer(self)
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v.visit(tree)
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v = _SigNameVisitor(self.symdict)
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v.visit(tree)
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self.inputs = v.inputs
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self.outputs = v.outputs
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self.inouts = v.inouts
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self.embedded_func = v.embedded_func
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@property
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@property
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def funcobj(self):
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def funcobj(self):
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return self.genfunc
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return self.genfunc
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@ -1,6 +1,6 @@
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import ast
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import ast
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from myhdl import intbv
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from myhdl._intbv import intbv
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from myhdl._Signal import _Signal, _isListOfSigs
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from myhdl._Signal import _Signal, _isListOfSigs
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