From a61daab43f317bd02c7a126ba24e52aedf08bc25 Mon Sep 17 00:00:00 2001
From: Keerthan Jaic <jckeerthan@gmail.com>
Date: Sat, 18 Jul 2015 09:39:06 -0400
Subject: [PATCH] add support for nvc for VHDL verification

https://github.com/nickg/nvc
---
 .gitignore                  | 1 +
 myhdl/conversion/_verify.py | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/.gitignore b/.gitignore
index 62e3790b..7fbe72d9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -22,6 +22,7 @@ modelsim.ini
 transcript
 *.log
 work/
+work_nvc/
 work_vlog/
 work_vcom/
 *.wlf
diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py
index 0474c231..795b8f32 100644
--- a/myhdl/conversion/_verify.py
+++ b/myhdl/conversion/_verify.py
@@ -55,6 +55,13 @@ registerSimulator(
     simulate="ghdl -r --workdir=work %(unitname)s"
     )
 
+registerSimulator(
+    name="nvc",
+    hdl="VHDL",
+    analyze="nvc --work=work_nvc -a pck_myhdl_%(version)s.vhd %(topname)s.vhd",
+    elaborate="nvc --work=work_nvc -e %(topname)s",
+    simulate="nvc --work=work_nvc -r %(topname)s"
+    )
 
 registerSimulator(
     name="vlog",